Verification Vector Generation Using Duplicate Command Elimination

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Solution Overview

Problem

The complexity of digital circuit design verification leads to large and inefficient verification vectors, with conventional rule-based compression techniques struggling to optimize the length and time of the verification process effectively.

Innovation Solution

An electronic device utilizing machine learning to generate optimized verification vectors by eliminating duplicate commands with the same state transition, reducing redundant operations, and selecting the vector with the smallest number of idle commands that maintains target coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If rule-based vector compression technique is used to reduce verification vector length, then the length of verification vector is reduced, but redundant verification processes cannot be eliminated and optimization is limited

Engineering Contradiction:

Improveverification vector lengthVSAvoidverification coverage

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

The patent extracts and eliminates duplicate commands from the verification vector by identifying commands that produce identical state transitions. The duplicate command eliminator module detects redundant commands and removes them, keeping only the first occurrence of each unique command sequence, thereby reducing vector length while preserving verification coverage.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of command repetition by using machine learning to identify optimal reduction ratios. The reduced vector generator module applies learned parameters to determine how many times to repeat commands, transforming the verification vector from a fixed-format structure to an optimized variable-length structure that maintains coverage while reducing size.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If machine learning is used to optimize verification vector, then the length is decreased and coverage is maintained, but additional processing time and complexity is introduced

Engineering Contradiction:

Improveverification efficiencyVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent performs preliminary training of the machine learning model using historical verification data before actual verification operations. The training module pre-processes and stores optimization patterns, so that during runtime, the duplicate command eliminator and reduced vector generator can quickly apply pre-learned rules without complex real-time computations, reducing operational complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an estimation model as an intermediary between the reduced vector generator and the verification process. This model predicts the coverage and quality of reduced vectors, allowing the system to evaluate multiple candidate vectors and select the optimal one without exhaustive verification, thereby managing complexity while maintaining high productivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If duplicate commands are eliminated to reduce verification vector size, then the number of operations is reduced, but it may affect the completeness of verification coverage

Engineering Contradiction:

Improvenumber of commandsVSAvoidverification coverage

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the verification results are continuously monitored and fed back to the machine learning model. The estimator evaluates whether eliminated duplicates truly maintain coverage, and the model adjusts its elimination strategy accordingly. This closed-loop feedback ensures that duplicate removal does not compromise verification completeness while maximizing compression.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11669773B2Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

Publication Date: 2023.06.06 SAMSUNG ELECTRONICS CO LTD

AI summary

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.