Verify Failbit Count Circuit Power Optimization
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Solution Overview
Problem
The power consumption of 3D NAND memory devices is high due to the inefficiencies in the verify failbit count (VFC) circuit, which is necessary for write verification in three-dimensional memory devices, as existing circuits lack optimization in counter management.
Innovation Solution
The implementation of a verify failbit count circuit that selectively turns on the most appropriate counters and turns off unnecessary ones based on the magnitudes of the verify failbit signal and reference currents, utilizing a hierarchy of bit counters (highest, lowest, and intermediate) to manage power consumption effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all counters in the VFC circuit are kept active to ensure complete verification coverage, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The verification process is divided into multiple segments corresponding to different bit positions (highest bit, intermediate bits, lowest bit). Each segment has its own counter that operates independently. The segmentation allows the system to activate only the necessary counter segments based on the actual verification needs, rather than keeping all counters active simultaneously.
Solution Approach 2:
The counter activation state is made dynamic rather than static. The control circuit dynamically adjusts which counters are active based on real-time verification conditions and the magnitude of verify failbit signals. This dynamic adaptation ensures that counters are activated only when needed for accurate measurement, reducing unnecessary power consumption while maintaining verification precision.
2Productivity
If multiple counters are activated simultaneously to handle different bit ranges, then productivity is improved, but device complexity increases
Solution Approach 1:
The verification circuit is segmented into multiple independent counter units, each responsible for specific bit ranges (highest bit counter, intermediate bit counters, lowest bit counter). This segmentation enables parallel processing of different bit ranges, improving verification productivity while keeping each individual counter unit relatively simple in structure.
Solution Approach 2:
The system activates only the necessary subset of counters based on the actual verification requirements rather than activating all counters simultaneously. The control circuit determines the appropriate scope of verification and activates only those counters needed for the current verification task, avoiding the complexity of managing all counters while still achieving high productivity when full verification is required.
Data Source
AI summary
A memory device includes a memory array and a count circuit coupled to the memory array. The count circuit includes a verify standard selector configured to output a verify standard signal, a bit counter circuit coupled to the verify standard selector and configured to receive the verify standard signal and output at least one comparison result, and a code converter coupled to the bit counter circuit.