Memory Column Repair Using Verify Read Cache
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Solution Overview
Problem
Existing column repair systems in memory systems face contention issues during read accesses, particularly during verify read operations, which can lead to increased costs and complexity when using dual-ported SRAM or larger SRAM sizes.
Innovation Solution
The implementation of a verify read cache and a normal read cache, with SRAM as the backing store, to service verify reads and normal reads respectively, reducing the need for SRAM access during write operations and allowing for asynchronous access management through arbitration circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-ported SRAM is used to service verify reads and normal reads simultaneously, then contention issues are resolved, but device complexity and cost increase
Solution Approach 1:
A verify read cache is introduced as an intermediary component between the SRAM and the verify read operation. The cache stores repair mapping information specifically for verify reads, allowing them to be serviced without accessing the SRAM during write operations. This mediator eliminates the contention between verify reads and normal reads for SRAM access, resolving the reliability issue without requiring dual-ported SRAM.
2Reliability
If SRAM size is increased to store repair mapping information for all address locations, then column repair capability is improved, but device complexity and cost increase
Solution Approach 1:
The repair mapping information storage is segmented into two parts: the SRAM stores repair mapping information for normal reads, while the verify read cache stores repair mapping information specifically for verify reads. This segmentation allows the SRAM to maintain a smaller size while still supporting full column repair capability, as the verify read cache handles the additional storage requirements for verify read operations.
Solution Approach 2:
Instead of expanding the SRAM size in a single dimension to accommodate all repair mapping information, the solution adds a new dimension by introducing a separate verify read cache. This cache operates in parallel with the SRAM, providing the needed storage capacity without increasing the SRAM footprint, thus maintaining simplicity while improving column repair capability.
3Reliability
If SRAM is accessed during verify read operations, then column repair is performed correctly, but access contention occurs during write operations
Solution Approach 1:
The verify read cache is pre-loaded with repair mapping information for verify reads before write operations begin. During write operations, the cache already contains the necessary repair mapping information, eliminating the need to access the SRAM during verify reads. This preliminary action ensures column repair accuracy is maintained while preventing access contention that would reduce write operation efficiency.
Data Source
AI summary
A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.