Verify-on-Write Storage Control for High-Throughput Flash Memory
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Solution Overview
Problem
Current data storage devices face challenges in achieving high throughput and efficient command execution while minimizing processing overhead, particularly in managing multiple memory chips and handling commands like read metadata, bad block scanning, copying data, and verifying writes.
Innovation Solution
A data storage device configuration with multiple memory boards and a controller board that processes commands in parallel, utilizing a high-speed interface like PCIe, and includes features such as error correction and bad block management to enhance performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are used to store large amounts of data, then storage capacity is improved, but command execution throughput deteriorates due to increased processing overhead
Solution Approach 1:
The system segments memory management into two distinct layers: a host driver that handles high-level data operations and a controller firmware that manages low-level memory chip operations. This segmentation allows the host to issue simplified commands while the controller handles the complexity of managing multiple memory chips, thereby maintaining high storage capacity without sacrificing command execution throughput.
Solution Approach 2:
The controller firmware acts as an intermediary between the host and the multiple memory chips. It receives commands from the host, processes them efficiently by managing the complexity of multiple chips, and returns results to the host. This intermediary layer shields the host from the overhead of directly managing multiple memory chips, preserving throughput while enabling large storage capacity.
2Quantity of substance
If the host directly manages multiple memory chips, then storage capacity is improved, but processing overhead on the host increases
Solution Approach 1:
The complex task of managing multiple memory chips is extracted from the host system and transferred to a dedicated controller firmware. The host only needs to interact with the controller through simplified interfaces, while the controller firmware handles all the complexity of addressing, reading, writing, and managing multiple memory chips. This extraction reduces host processing overhead while maintaining the ability to manage large storage capacities.
Solution Approach 2:
The controller firmware provides self-service by autonomously managing all operations related to multiple memory chips without requiring direct host intervention. It handles command processing, data transfer, and memory chip coordination independently, allowing the host to focus on higher-level tasks while the controller handles the detailed work of managing expanded storage capacity.
3Reliability
If traditional read-write command sequences are used for data copying, then data integrity is improved, but command execution time increases
Solution Approach 1:
The system performs preliminary verification of data integrity through metadata checks before initiating copy operations. The driver and controller validate data integrity in advance using checksums or error detection codes stored in metadata, allowing the actual copy operation to proceed without time-consuming verification steps during execution. This preliminary action ensures data integrity while reducing overall command execution time.
Data Source
AI summary
A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a verify on write command from the host using the interface, write data to one of the memory devices, read the data from the memory device, calculate an error correction code for the data as the data is being read, verify the data was written correctly to the memory device using the error correction code and communicate results to the host using the interface.