Vernier DAC Architecture Using Split-Bit Reference Scaling
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Solution Overview
Problem
Current digital-to-analog converters (DACs) face limitations in conversion accuracy due to manufacturing errors, environmental factors, and noise, which restrict the maximum achievable accuracy to around 18 to 22 binary bits, and existing methods do not effectively enhance accuracy beyond these limits.
Innovation Solution
The proposed method employs a Vernier digital-to-analog conversion technique, where a control code is divided into high-order and lower-order bits, with the latter being digitally multiplied and then converted using two parallel DACs, allowing for a fractional ratio of reference signals to improve accuracy without stringent requirements on DAC elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital-to-analog conversion methods are used, then the conversion accuracy is limited to 18-22 binary bits, but increasing the accuracy beyond this limit requires advanced manufacturing techniques and stringent precision demands on DAC components
Solution Approach 1:
The control code is divided into high-order bits and lower-order bits, which are processed separately through different conversion paths. The high-order bits are converted using a first DAC with a first reference signal, while the lower-order bits are converted using a second DAC with a second reference signal. This segmentation allows each DAC to operate with relaxed precision requirements while achieving high overall conversion accuracy through the combination of both conversion results.
2Measurement precision
If the number of bits in the control code is increased to improve accuracy, then the conversion accuracy improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of using a single complex high-resolution DAC, the system segments the conversion task into two separate DACs handling different bit portions. This reduces the complexity of individual DAC components while maintaining high overall accuracy through the segmented conversion architecture.
Solution Approach 2:
The patent introduces a new dimension to the conversion process by using two different reference signals with a fractional ratio relationship. This dimensional approach allows the system to achieve high accuracy not through increased bit depth in a single converter, but through the coordinated operation of multiple converters with different reference signals.
Data Source
AI summary
A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a−αN bits of the control code X by aα times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a−αN of the control code X being a result of multiplication by aα times, according to formula Q=M±N, wherein N is a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y1 to an analog signal Z1, and converting the resulting digital code N from a reference signal Y2 to an analog signal Z2, wherein reference signals Y1 and Y2 are related by a ratio: Y2=Y1 (1±a−α), wherein a is a base of number system, α is a number of bits of shifting the control code a−αN; and summing analog signals Z1 and Z2 to generate an analog output signal Z0.