Vernier Delay Line Summation Read-Out for TDC Resolution

The patent inverts the conventional priority read-out approach by using summation read-out instead. Instead of identifying the first stage with a specific condition (priority encoding), it sums the outputs of all stages to determine the time difference. This inversion allows non-monotonic delay lines to contribute all their stages to the measurement, resolving the contradiction between simple circuit structure and measurement precision.

The patent implements feedback through iterative calibration processes that measure and compensate for non-monotonic behavior. By repeatedly measuring the delay characteristics and adjusting the calibration values, the system converges to accurate time difference measurements despite the complex non-monotonic stage behavior. This feedback mechanism resolves the contradiction by maintaining linearity while accommodating complex stage behavior.

The patent employs periodic calibration actions that occur at optimized intervals rather than continuously. By periodically updating calibration values and using efficient summation read-out, the system maintains high resolution from multiple stages while minimizing the impact on re-trigger rate. This periodic approach resolves the contradiction by balancing measurement precision with speed.

The patent replaces the conventional parallel read-out mechanism with a summation-based approach that eliminates the need for complex buffer propagation. By summing the outputs of all stages directly without requiring synchronized parallel propagation through multiple buffers, the system achieves fast sampling rates without being constrained by buffer propagation times. This substitution resolves the contradiction between productivity and time loss.