Vernier PLL Counter Synchronization for Asynchronous Time Measurement
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Solution Overview
Problem
Current digital time measurement techniques, such as DDMTD, require synchronized clocks to achieve high precision, limiting their applicability to asynchronous clock domains.
Innovation Solution
A vernier phase locked loop system that generates reference clocks from a common external clock, allowing measurement of elapsed time between events in multiple asynchronous clock domains using vernier phase locked loops and a vernier phase error detector, which synchronize counters across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DDMTD technique is used to achieve high precision time measurement, then measurement precision is improved, but the requirement for syntonized clocks limits adaptability to asynchronous clock domains
Solution Approach 1:
The patent introduces a vernier reference clock as an intermediary element that mediates between the target clock and the measurement system. This vernier reference clock, which operates at a slightly different frequency than the target clock, enables time transfer and measurement between asynchronous clock domains by creating a beat frequency that can be measured and used to calculate time differences, thus resolving the contradiction between maintaining high precision and achieving adaptability to asynchronous domains
Solution Approach 2:
The patent changes the frequency parameter of the reference clock to be slightly different from the target clock frequency, creating a vernier effect. This parameter change enables the system to measure time in asynchronous domains by exploiting the beat frequency generated by the frequency difference, thereby achieving both precision and adaptability
2Measurement precision
If syntonized clocks are used in DDMTD, then measurement precision is improved, but device complexity increases due to the requirement for common clock source and frequency matching
Solution Approach 1:
The patent extracts the strict frequency matching requirement from the measurement system by introducing a vernier reference clock with a deliberately different frequency. This extraction allows the system to achieve high precision time measurement without requiring syntonized clocks, thereby reducing device complexity while maintaining measurement precision
Data Source
AI summary
An apparatus that measures elapsed time in digital systems with multiple clocks includes a vernier reference (VREF) configured to generate a reference counter signal with a numeric output and two reference clock signals. The apparatus also includes a plurality of synchronizer VPLLs configured to receive the reference counter signal and the two reference clock signals and generate a plurality of synchronized counters, each synchronized counter being co-linear with the reference counter and operating in a respective target clock domain.