Vernier TDC Gain Calibration in PLLs for Clock-Domain Synchronization
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Solution Overview
Problem
PLLs in different clock domains of an integrated circuit respond differently to reference clock jitter due to varying loop bandwidths, leading to synchronization degradation and potential communication failures.
Innovation Solution
Incorporating a time-to-digital converter (TDC) gain calibration circuit in each PLL to calibrate the TDC circuit to a nominal gain, ensuring a consistent jitter response across all clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PLLs in different clock domains use different loop bandwidths, then each PLL can be optimized for its specific application, but the jitter response varies across clock domains causing synchronization degradation
Solution Approach 1:
The patent changes the TDC gain parameter through calibration to achieve a desired loop bandwidth. The calibration circuit adjusts the TDC gain by modifying the time increment length, thereby controlling the loop bandwidth to a target value. This allows each PLL to be calibrated to have consistent jitter response characteristics across different clock domains, resolving the synchronization issue while maintaining adaptability.
2Measurement precision
If TDC gain varies due to manufacturing conditions and circuit environment, then PLL performance can be optimized for specific conditions, but synchronization degrades when gains differ across clock domains
Solution Approach 1:
The patent implements a feedback-based calibration mechanism where the calibration circuit measures the actual TDC gain and adjusts it to match a target value. The calibration circuit receives feedback about the time difference measurement and modifies the TDC gain accordingly. This closed-loop approach compensates for manufacturing variations and environmental effects, ensuring consistent synchronization performance across all clock domains.
Solution Approach 2:
The patent performs TDC gain calibration as a preliminary action before normal PLL operation. The calibration circuit pre-adjusts the TDC gain to the desired value during an initialization or calibration phase, ensuring that subsequent operation maintains consistent synchronization characteristics across clock domains despite manufacturing variations.
3Stability of the object's composition
If reference clock jitter is present, then frequency stability can be maintained, but timing differences cause PLL output clock edge disturbances and potential communication failures
Solution Approach 1:
The patent changes the loop bandwidth parameter through TDC gain calibration to optimize the PLL's jitter response. By carefully selecting and calibrating the loop bandwidth, the PLL can maintain frequency stability while filtering reference clock jitter to prevent output clock edge disturbances. This parameter optimization ensures that communication reliability is maintained even in the presence of reference clock jitter.
Data Source
AI summary
In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.