Vernier Time Difference Circuit for High-Resolution Low-Power TDCs
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in achieving high resolution and low power consumption, particularly in fractional-N All-Digital Phase-Locked Loops (ADPLLs), due to limitations in delay line technology and high power consumption from high-frequency feedback signals.
Innovation Solution
A time difference determining device utilizing a Vernier technique with dual delay lines and samplers, where one delay line has faster cells and the other slower cells, allowing for high resolution and low power consumption by using a lower frequency sampling signal, and an output stage to determine the leading signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a standard delay line TDC architecture is used, then the device is simple to implement, but the resolution is limited by the minimum delay of buffers which is too high for many applications
Solution Approach 1:
The TDC is divided into two separate branches (first and second time difference determining branches), each with its own delay lines and samplers. This segmentation allows independent optimization of each branch's delay characteristics, enabling high resolution measurement while maintaining manageable complexity in each individual branch.
Solution Approach 2:
The patent transitions from a single delay line approach to a two-dimensional structure with two branches having different delay characteristics. The first branch uses delay cells with first delay values while the second branch uses delay cells with second delay values, creating an additional dimension in the measurement space that enables higher resolution without proportionally increasing complexity.
2Speed
If the DCO feedback frequency is kept high, then the PLL operates at high frequency, but the power consumption is very high due to the high frequency of the clock DCOFB
Solution Approach 1:
The patent employs periodic sampling where the second digital signal (lower frequency) periodically samples the delayed versions of the first digital signal. This periodic action at a lower frequency reduces the power consumption of the sampling operation while still capturing the time difference information, as the sampling occurs only at necessary intervals rather than continuously at the high DCO feedback frequency.
3Measurement precision
If a Vernier TDC is used to improve resolution, then the TDC resolution is significantly improved and independent from technology, but there is no power consumption reduction
Solution Approach 1:
The Vernier TDC is segmented into two independent branches with different delay characteristics. The first branch uses delay cells with first delay values and the second branch uses delay cells with second delay values. This segmentation allows each branch to operate at optimized frequencies, with the second branch sampling at a lower frequency to reduce power consumption while the first branch maintains high resolution capability.
Solution Approach 2:
The patent changes the operating parameters of the two branches differently - the first branch operates with delay cells having first delay values at one frequency, while the second branch operates with delay cells having second delay values at a lower frequency. This parameter differentiation enables the system to achieve high resolution through the Vernier effect while reducing overall power consumption by operating one branch at lower frequency.
4Use of energy by moving object
If DCO downconversion is used to reduce power consumption, then the power consumption is reduced by shifting down the DCO feedback frequency, but the resolution decreases by a factor of 2 and matching of delays becomes difficult
Solution Approach 1:
Instead of downconverting a single TDC input, the patent segments the system into two branches where the first branch processes the original high-frequency signal for resolution-critical measurements, while the second branch processes a downconverted lower-frequency signal for power-efficient sampling. This segmentation allows the system to maintain high resolution in the first branch while achieving power reduction in the second branch, avoiding the resolution loss that would occur in a single downconverted system.
Data Source
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AI summary
A time difference determining device determines a time difference between a first digital signal and a second digital signal. It comprises a first time difference determining branch, comprising a first delay line, in turn comprising N first delay cells, each of the N first delay cells having a first delay, and a second delay line, comprising N second delay cells, each of the N second delay cells having a second delay, the second delay (f) being higher than the first delay. Moreover, it comprises a second time difference determining branch, in turn comprising a third delay line comprising N third delay cells, each of the N third delay cells having a second delay, and a fourth delay line, comprising N fourth delay cells, each of the N fourth delay cells having the first delay.