Vertex Index Routing in Two-Level Primitive Binning

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Solution Overview

Problem

Existing hardware-accelerated three-dimensional graphics processing technologies face inefficiencies in rendering operations due to suboptimal organization and management of geometry data, leading to increased memory access latency and power consumption.

Innovation Solution

Implementing a two-level primitive batch binning technique that organizes geometry data into coarse and fine bins, enhancing temporal and spatial cache locality by reordering and compressing data for efficient rendering operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If geometry data is organized using traditional methods, then device complexity is reduced, but memory access latency increases and rendering performance deteriorates

Engineering Contradiction:
Improverendering performanceVSAvoidmemory access latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides geometry data into two hierarchical levels: coarse bins that group primitives by screen space region, and fine bins that further organize vertices within each coarse bin. This segmentation enables localized memory access patterns, reducing latency by avoiding full-geometry traversals and improving rendering throughput through better data locality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary organization of geometry data into coarse and fine bins before rendering operations. By pre-sorting primitives and vertices into spatially coherent groups, the system eliminates the need for runtime sorting and reduces memory access latency during actual rendering, thereby improving overall productivity.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If geometry data is reorganized into coarse and fine bins, then memory access latency is reduced, but device complexity increases

Engineering Contradiction:
Improvememory access latencyVSAvoiddata organization complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent divides geometry data into two hierarchical levels: coarse bins that group primitives by screen space region, and fine bins that further organize vertices within each coarse bin. This segmentation enables localized memory access patterns, reducing latency by avoiding full-geometry traversals and improving rendering throughput through better data locality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The geometry reordering and compression unit automatically performs the binning operations using the primitive data and vertex indices it receives. The system is self-sufficient in organizing its own data without requiring external intervention, thereby managing the increased complexity internally while presenting a simplified interface to other pipeline stages.

Inventive Principle:
Principle #25Self-service

3Productivity

If vertex index information is joined with primitives in coarse binning mode, then spatial cache locality is improved, but processing complexity increases

Engineering Contradiction:
Improvecache localityVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges vertex index information with primitive data during the coarse binning stage. By combining these related data structures early in the pipeline, the system creates a unified representation that improves spatial cache locality, as adjacent primitives and their vertices are stored together, reducing memory access complexity in subsequent fine binning operations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12406425B2Vertex index routing for two level primitive batch binning
Publication Date: 2025.09.02 ADVANCED MICRO DEVICES INC
  • US12406425B2 patent drawing
  • US12406425B2 patent drawing
  • US12406425B2 patent drawing

AI summary

Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler. The techniques also include initiating a fine binning pass in which the sorted set of draw calls is processed through the world-space pipeline and the screen-space pipeline.