Two-Terminal Vertical 1T-DRAM Structure for Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM technologies face challenges in scaling down due to physical limitations, particularly the need for a gate terminal in three-terminal thyristor-based 1T-DRAM structures, which increases area requirements and limits further miniaturization.
Innovation Solution
A two-terminal vertical 1T-DRAM is developed with a base region having adjustable doping concentrations between 1×10^18 cm^-3 to 1×10^19 cm^-3, allowing for latch-up voltage increase and 'high' state recording, and between 1×10^16 cm^-3 to 1×10^17 cm^-3 for 'low' state recording, without the need for a gate terminal, using a laminated structure of high- and low-concentration semiconductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three-terminal thyristor-based 1T-DRAM structure is used, then the memory operation can be performed with p-n-p-n structure, but the area required increases due to horizontal formation and gate terminal requirement
Solution Approach 1:
The patent transitions from horizontal formation to vertical formation of the p-n-p-n thyristor structure. The semiconductor layers are stacked vertically with the first conductive type layer, second conductive type layer, third conductive type layer, and fourth conductive type layer arranged in vertical sequence, enabling three-dimensional integration and reducing planar area occupation.
Solution Approach 2:
The gate terminal is removed from the three-terminal thyristor structure to create a two-terminal configuration. The patent achieves memory operation by applying voltage directly between the first and fourth conductive type layers, eliminating the need for the gate terminal and reducing structural complexity and area requirements.
2Productivity
If design rule is scaled down to 10 nm or less, then the degree of integration can be increased to 1 terabit, but physical limitations including bridge phenomenon occur
Solution Approach 1:
The vertical stacking of semiconductor layers creates a three-dimensional structure that reduces the lateral design rule requirements. By transitioning from two-dimensional planar integration to three-dimensional vertical integration, the patent achieves higher density without suffering from the bridge phenomenon that plagues scaled-down lateral structures.
Solution Approach 2:
The patent embeds multiple functional layers within a vertical stack, where each layer serves a specific purpose in the thyristor operation. The nested structure of alternating conductive type layers creates the necessary p-n-p-n configuration in a compact vertical space, enabling high integration without lateral scaling limitations.
3Productivity
If capacitor height is increased to achieve higher integration, then storage capacity improves, but bridge phenomenon between cylinder-type capacitors occurs
Solution Approach 1:
The patent completely eliminates the capacitor component from the memory cell structure by using a thyristor-based 1T-DRAM configuration. The thyristor itself provides both storage and read/write functionality through its bistable states, removing the need for separate capacitor structures and eliminating the bridge phenomenon issue entirely.
Solution Approach 2:
The thyristor structure performs multiple functions: it serves as both the storage element (through its bistable latching behavior) and the access transistor. This multi-functional design replaces the traditional separate capacitor and transistor configuration, achieving high integration without the physical limitations of tall capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-terminal vertical 1T-DRAM achieves reduced thickness and area requirements, enabling efficient read and write operations without a gate terminal, overcoming physical limitations of conventional DRAM technologies and potentially replacing 10 nm-scale DRAMs.
Implementation Method 1
a base region including a first-type low-concentration semiconductor layer and a second-type low-concentration semiconductor layer, wherein a doping concentration of the base region is adjusted
Implementation Method 2
when the doping concentration of the base region increases from 1×10^18 cm^-3 to 1×10^19 cm^-3, latch-up is generated according to increase in the doping concentration of the base region, and a latch-up voltage is increased
Data Source
AI summary
The present invention discloses a two-terminal vertical 1T-DRAM and a method of fabricating the same. According to one embodiment of the present invention, the two-terminal vertical 1T-DRAM includes a cathode layer formed of a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.