Vertical 1T1R Memory Cell Layout for Higher Embedded Density
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Solution Overview
Problem
Conventional embedded memory designs are limited by the large area of access transistors, which reduce cell density and increase costs, and etching processes can damage memory device surfaces, affecting reliability.
Innovation Solution
A vertically stacked access transistor design with a smaller profile is implemented, using a pillar structure for the channel material and a dielectric layer to separate memory cells, allowing for a denser layout and reducing the overall area of each memory cell to 4F^2 compared to conventional 25F^2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional access transistor design is used, then transistor functionality is achieved, but cell area becomes large (25F^2)
Solution Approach 1:
The patent transitions from a planar transistor layout to a vertical stacked configuration, moving the transistor components into the third dimension. The channel extends vertically between source and drain regions, with the gate wrapping around the channel in a cylindrical or planar gate configuration, achieving compact area while maintaining transistor control functionality
Solution Approach 2:
The gate structure is nested around the channel in a wrap-around configuration, with the gate enclosing the channel vertically. This nested arrangement allows the gate to control the channel from multiple directions while occupying minimal planar space, resolving the contradiction between compact area and effective transistor control
2Reliability
If etching process is used to define memory device boundaries, then device patterning is achieved, but surface damage occurs affecting reliability
Solution Approach 1:
The patent replaces the mechanical etching process with a deposition-based definition method. Memory device boundaries are defined by depositing dielectric or conductive materials in specific patterns rather than removing material through etching, thereby avoiding surface damage while achieving precise device patterning
Solution Approach 2:
The patent performs preliminary deposition of defining layers before final device formation. By pre-defining boundaries through material deposition and using these as templates for subsequent processing steps, the method avoids the need for damaging etching operations while maintaining manufacturing precision
Data Source
AI summary
Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.