Vertical 1T1R RRAM Cell Layout for Higher Memory Density
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Solution Overview
Problem
The existing 1T1R resistive random access memory has limited memory density due to the difficulty in reducing the area of the transistor, which restricts the miniaturization of the memory cell.
Innovation Solution
The 1T1R resistive random access memory design features a transistor with a channel layer, gate layer, and vertically distributed drain and source layers, reducing the transistor's footprint to 4F^2, and includes a resistance switching device connected to the drain layer and bit line, with a gate layer connected to the word line and source layer connected to the source line, along with additional dielectric and metal layers for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional planar transistor structure is used in 1T1R memory cell, then the transistor can be easily manufactured with standard processes, but the memory cell area becomes large which limits memory density
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure by stacking the source, channel, and drain layers in the vertical direction. This dimensional change allows the transistor to achieve its function in a smaller footprint area, directly resolving the contradiction between ease of manufacture and memory cell area reduction.
Solution Approach 2:
The vertical transistor structure nests the channel layer between the source and drain layers in the vertical direction, creating a compact stacked configuration. This nesting arrangement enables the transistor components to occupy overlapping vertical space rather than horizontal space, reducing the overall memory cell footprint while maintaining manufacturability.
2Area of stationary object
If the transistor area is reduced to increase memory density, then memory density improves, but the transistor becomes difficult to manufacture with existing processes
Solution Approach 1:
By moving to a vertical stacking architecture, the patent achieves area reduction without compromising manufacturability. The vertical configuration uses standard thin-film deposition and etching processes to create stacked layers, making the reduced-footprint transistor as manufacturable as conventional planar transistors.
Solution Approach 2:
The transistor is segmented into distinct vertical layers (source layer, channel layer, drain layer) that can be independently formed using standard semiconductor manufacturing processes. This segmentation allows each layer to be optimized and manufactured separately, facilitating ease of production despite the compact vertical integration.
Data Source
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AI summary
The present application provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The application reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory, and thus solving the problem of the existing 1T1R resistive random access memory that the memory density is limited due to that the area of the transistor cannot be reduced.