Vertical 2D Nanosheet Channels for High-Density 3D Transistors
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Solution Overview
Problem
Current semiconductor device fabrication techniques are facing challenges in scaling transistors to single-digit nanometer nodes, leading to a desire for three-dimensional (3D) semiconductor circuits where transistors can be stacked on top of each other.
Innovation Solution
The development of a semiconductor device featuring pair of channel structures made from two-dimensional (2D) semiconductor material oriented perpendicular to the substrate, with source/drain structures on either side and a gate structure in between, allowing for vertical stacking and precise nanosheet channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional 2D fabrication techniques are used, then manufacturing processes are well-established, but transistor density and scaling to single-digit nanometer nodes are limited
Solution Approach 1:
The patent transitions from traditional 2D planar transistors to 3D vertically-stacked nanosheet transistors. Multiple channel structures are stacked vertically above the substrate, enabling increased transistor density without proportionally increasing the footprint area. This dimensional change allows scaling to single-digit nanometer nodes by utilizing the vertical dimension for additional transistor stacking.
2Productivity
If 3D vertically-stacked transistor structures are implemented, then transistor density increases, but fabrication process complexity increases
Solution Approach 1:
The channel structure is segmented into multiple discrete nanosheets stacked vertically. Each nanosheet can be independently formed and controlled, allowing for modular fabrication. The segmentation enables precise control over each layer's properties while maintaining overall 3D stacking architecture, reducing the complexity of forming the entire structure as a single unit.
Solution Approach 2:
The patent employs preliminary patterning and deposition steps to prepare the substrate and form sacrificial structures before creating the final nanosheet channels. Core structures are formed first, followed by shell structure deposition, and then selective removal to create the channel cavities. This sequential preliminary action simplifies the overall fabrication by breaking down complex 3D formation into manageable stages.
3Reliability
If channel structures are formed with precise nanosheet dimensions, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The fabrication process utilizes self-aligned deposition and etching techniques where previously formed structures serve as alignment references for subsequent steps. The core structures automatically define the position and dimensions of the shell structures, eliminating the need for separate alignment operations. This self-service approach maintains precise nanosheet dimensions while reducing the overall manufacturing precision burden.
4Productivity
If complex masking steps are reduced, then manufacturing efficiency improves, but patterning precision may be compromised
Solution Approach 1:
Sacrificial core structures are formed in advance with precise dimensions and positions. These pre-formed cores serve as templates that automatically define the final channel locations and dimensions. By performing this patterning action preliminarily, the need for multiple subsequent masking steps is eliminated, maintaining both manufacturing efficiency and patterning precision.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a pair of channel structures each configured to have a current direction along a first direction substantially parallel to a working surface of a substrate. The semiconductor device also includes source/drain (S/D) structures on opposing sides of the pair of channel structures along the first direction. The semiconductor device further includes a gate structure between the pair of channel structures. The pair of channel structures includes two-dimensional (2D) semiconductor material oriented substantially perpendicular to the working surface of the substrate.