Vertical 2D Material Transistors With Seeded Single-Crystal Channels
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Solution Overview
Problem
Conventional methods for forming two-dimensional (2D) materials as channel regions in transistors result in crystalline defects, affecting the electrical characteristics of semiconductor devices, and are challenging due to topography issues in vertical FETs, especially when attempting to achieve high-quality crystalline structures without damaging exposed components.
Innovation Solution
The use of crystalline aluminum oxide as a seed material to form high-quality 2D materials, which are grown on its sidewalls, reducing crystalline defects and allowing for the formation of single-crystal 2D channel regions with improved band gap and mobility properties, while maintaining compatibility with conventional semiconductor fabrication techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 2D material is grown directly on substrate to form channel region, then large area coverage is achieved, but crystalline defects increase
Solution Approach 1:
A crystalline seed layer is introduced as an intermediary between the substrate and the 2D material channel region. This seed layer provides a high-quality crystalline template that enables epitaxial growth of defect-free 2D materials over large areas, resolving the contradiction between coverage area and crystalline quality.
2Manufacturing precision
If thermal anneal process is applied to reduce crystalline defects, then crystalline quality improves, but exposed components are damaged
Solution Approach 1:
The crystalline seed layer is formed before growing the 2D material channel region, establishing a high-quality crystalline foundation in advance. This preliminary action eliminates the need for subsequent thermal annealing processes that would damage exposed components, while still achieving the desired crystalline quality through epitaxial growth.
3Ease of manufacture
If conventional methods are used to form 2D material on vertical FET, then fabrication is simplified, but topography challenges prevent high-quality formation
Solution Approach 1:
The crystalline seed layer is selectively formed only in regions where high-quality 2D material growth is required, such as on the sidewalls of vertical FET structures. This localized approach maintains fabrication simplicity while achieving high crystalline quality where needed, by adapting the seed layer formation to the specific topography of vertical FETs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of transistors with reduced crystalline defects, enhanced electrical performance, and compatibility with existing semiconductor processes, improving the quality of 2D material-based channel regions in vertical FETs.
Implementation Method 1
The 2D material of the transistor is a single crystal material and the transistor exhibits a higher quality (e.g., reduced crystalline defects) compared to a conventional transistor where the 2D material is formed directly on the substrate or other material
Data Source
AI summary
An apparatus including an array of memory cells comprising transistors is disclosed. One or more of the transistors comprise a crystalline material extending substantially transverse to a base material. A gate dielectric material is adjacent to the crystalline material. A two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. The gate dielectric material overlies additional portions of the two-dimensional material of the channel region. One or more gates are adjacent to the gate dielectric material. An electronic device is also disclosed comprising one or more of the transistors. The one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. The channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.