Vertical 2D Material Transistor for Packing Density
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Solution Overview
Problem
Current silicon-based transistors face challenges in scaling down due to increased effective resistance and variability in threshold voltage as fin width decreases, leading to reduced carrier mobility and performance inconsistencies in FinFETs.
Innovation Solution
Implementing two-dimensional (2-D) materials, such as graphene, phosphorene, and transition metal dichalcogenides, in vertical semiconductor structures to form channel regions, which offer high carrier mobility and allow for compact double-gate architectures, eliminating the need for source/drain doping and enabling precise gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin width is decreased to scale down transistor size, then packing density is improved, but effective resistance increases and carrier mobility decreases
Solution Approach 1:
The patent transitions from planar 2-D material channels to vertical 3-D standing wave channels, utilizing the vertical dimension to increase channel length and control volume without increasing lateral footprint. This dimensional change allows maintaining low resistance while preserving compact packing density.
Solution Approach 2:
The patent employs composite material structures combining 2-D materials (graphene, phosphorene, TMDs) with 3-D vertical channel geometries, creating hybrid structures that leverage the high mobility of 2-D materials with the enhanced control and lower resistance of vertical 3-D configurations.
2Productivity
If fin width is decreased to scale down transistor size, then packing density is improved, but threshold voltage variability increases
Solution Approach 1:
By standing the channel up in the vertical dimension, the patent achieves longer effective channel lengths for gate control without reducing lateral dimensions, providing better electrostatic control and reduced threshold voltage variability while maintaining high packing density.
Solution Approach 2:
The vertical channel structure nests multiple functional regions (source, drain, channel, gate) within a compact lateral footprint by extending in the vertical dimension, allowing complex transistor structures to be integrated densely while maintaining precise electrical characteristics.
3Ease of manufacture
If conventional silicon-based FinFET structures are used, then manufacturing maturity is maintained, but carrier mobility is limited and performance scaling is hindered
Solution Approach 1:
The patent combines the manufacturing advantages of established FinFET processes with emerging 2-D materials (graphene, phosphorene, TMDs), creating composite structures that inherit process compatibility while achieving superior carrier mobility and performance scaling.
Solution Approach 2:
The patent changes the material parameter from conventional silicon to 2-D materials with inherently higher carrier mobility, while simultaneously changing the geometric parameter from planar to vertical channel configuration, achieving performance enhancement without sacrificing manufacturability.
Data Source
AI summary
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.