Multi-Channel 2DEG Transistor Structure for Higher Power Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing transistors using silicon face limitations in conducting high power and efficiency, while wider bandgap semiconductor materials like SiC, AlN, and ZnO offer improved performance but require innovative structures to optimize current flow and reduce on-resistance.
Innovation Solution
A transistor structure utilizing multiple two-dimensional electron gas (2DEG) layers below the surface, connected by conductive paths and controlled by a gate terminal, allowing for reduced on-resistance and potentially functioning as multiple independently controllable transistors sharing a common source and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single-channel HEMT structure is used, then the device complexity is low, but the power handling capacity and efficiency are limited
Solution Approach 1:
The patent divides the transistor channel into multiple independent 2DEG channels stacked vertically, each capable of conducting current independently. This segmentation allows the device to handle higher power by summing the current capacity across multiple channels while maintaining a relatively compact structure that doesn't linearly increase device complexity
Solution Approach 2:
The patent transitions from a planar single-channel structure to a three-dimensional multi-channel stack, utilizing the vertical dimension to accommodate multiple 2DEG channels. This dimensional change enables increased power handling capacity without proportionally increasing the lateral device footprint or overall complexity
2Reliability
If multiple heterojunction layer sets are stacked vertically, then the on-resistance is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements a nested structure where multiple heterojunction layer sets are stacked vertically, with each layer containing a barrier semiconductor layer and channel semiconductor layer. The conductive source plug and drain plug extend through all layers, nesting the electrical connections through the entire stack. This nested configuration reduces on-resistance by providing multiple parallel conduction paths while using standardized repeating units that can be manufactured with consistent precision
Solution Approach 2:
The patent changes the structural parameter from a single heterojunction interface to multiple stacked interfaces, creating parallel current paths. By changing the architecture from two-dimensional planar to three-dimensional vertical stacking, the on-resistance is reduced through increased conduction area without requiring proportionally tighter manufacturing tolerances on individual layer parameters
3Loss of energy
If a multi-channel HEMT structure is implemented, then the efficiency is improved, but the ease of manufacture decreases
Solution Approach 1:
The patent creates a universal repeating unit consisting of a barrier semiconductor layer and channel semiconductor layer that forms a complete functional 2DEG channel. Each unit is identical and performs the same function, allowing the structure to be manufactured by repeating the same fabrication process steps multiple times. This universality improves efficiency through multiple channels while maintaining ease of manufacture through process repetition rather than requiring different manufacturing steps for each channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure significantly reduces on-resistance and enables independent control of multiple transistors, enhancing power handling capacity and efficiency.
Implementation Method 1
a first heterojunction formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer, the first heterojunction inducing a first two-dimensional electron gas (2DEG) within the first channel semiconductor layer
Implementation Method 2
the first heterojunction inducing a first two-dimensional electron gas (2DEG) within the first channel semiconductor layer
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.