Vertical 2DEG HEMT Structure for High-Mobility Nitride Channels
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Solution Overview
Problem
Existing semiconductor devices based on Group III nitride semiconductors face limitations due to defects and substrate compatibility issues, restricting their application ranges, especially in high energy, high voltage, or high frequency applications.
Innovation Solution
A semiconductor device with a vertical interface and channel layers is proposed, featuring a hexagonal crystalline lattice structure, where a vertical two-dimensional electron gas (2DEG) or hole gas (2DHG) is formed adjacent to the interface between the channel and channel supply layers, using substrates like Si, Al2O3, or SiC, and incorporating a buffer and nucleation layer for improved crystal quality and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional horizontal interface structures are used, then fabrication is simpler, but conductivity and response speed are limited
Solution Approach 1:
The patent transitions from conventional horizontal interfaces to vertical interfaces by changing the growth direction and interface orientation. The channel layer and channel supply layer are arranged vertically with their interface perpendicular to the substrate surface, enabling spontaneous formation of 2DEG or 2DHG at the vertical interface, thereby achieving high conductivity and response speed while maintaining fabrication feasibility through epitaxial growth
2Reliability
If doping effects are used to enhance conductivity, then charge carrier concentration increases, but ion scattering increases and mobility decreases
Solution Approach 1:
The patent utilizes the spontaneous polarization effect inherent to Group III nitride semiconductors at vertical interfaces to automatically generate high-density 2DEG or 2DHG without requiring external doping. The system self-generates the necessary charge carriers through the polarization field at the vertical interface between channel and channel supply layers, achieving high conductivity while avoiding ion scattering and maintaining high carrier mobility
3Reliability
If Group III nitride semiconductors are used, then high breakdown electric field and wide forbidden band are achieved, but substrate compatibility and defect issues arise
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the substrate and the channel/channel supply layers. This buffer layer mediates the lattice mismatch and thermal expansion coefficient differences between the substrate and Group III nitride semiconductor layers, reducing defect formation and improving substrate compatibility while preserving the high breakdown electric field and wide forbidden band characteristics of the nitride semiconductor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure enhances conductivity and response speed, overcoming substrate limitations and increasing the application range of Group III nitride semiconductors in high mobility transistors, while reducing ion scattering and doping effects, leading to better performance in high energy and frequency applications.
Implementation Method 1
Fixed polarized charges are present at a surface of the polar semiconductor or at an interface of two different polar semiconductors. These fixed polarized charges may attract movable electrons or hole carriers, thus forming a two-dimensional electron gas 2DEG or a two-dimensional hole gas 2DHG.
Data Source
AI summary
The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein at least one of a vertical two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.