Vertical 2DEG Semiconductor Structure for Higher Withstand Voltage
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Solution Overview
Problem
Existing semiconductor devices with group III nitride semiconductors face limitations due to defects that restrict their application, particularly in high energy, high voltage, or high frequency applications, and the influence of substrates like silicon substrates on device performance.
Innovation Solution
A semiconductor device with a dual-channel structure featuring vertical 2DEG or 2DHG heterojunctions, electrodes positioned on both sides of the heterojunctions, and a method that allows for partial or complete removal of the substrate, enhancing withstand voltage and circuit interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor structure with group III nitride semiconductors is used, then the device can be manufactured with existing processes, but the device performance is limited by defects and substrate influence in high energy, high voltage, or high frequency applications
Solution Approach 1:
The patent divides the semiconductor structure into multiple segments including a first channel layer, a first barrier layer forming a first heterojunction, a second channel layer, and a second barrier layer forming a second heterojunction. This segmentation creates multiple vertical 2DEG channels that work together to improve overall device performance while allowing each segment to be optimized independently for high voltage and high frequency operation
Solution Approach 2:
The patent transitions from conventional horizontal device structures to a vertical heterojunction architecture where the channel and barrier layers are stacked vertically to form vertical interfaces. This dimensional change enables the formation of vertical 2DEG channels that provide superior electrical characteristics and allow electrodes to be positioned on both upper and lower sides of the heterojunction, improving current flow and voltage withstand capability
2Reliability
If the substrate is retained in the semiconductor device, then the device structure is simpler to manufacture, but the substrate (particularly heterogeneous substrates) negatively influences device performance and heat dissipation
Solution Approach 1:
The patent extracts and removes the substrate from the final semiconductor device structure. The manufacturing process includes forming the complete heterojunction structure on a substrate, then removing the substrate to leave a suspended or supported structure without the original substrate. This extraction eliminates the negative influence of heterogeneous substrates on device performance and improves heat dissipation, while the manufacturing process integrates substrate removal as a standard step
3Power
If electrodes are positioned only on one side of the heterojunction, then the device structure is simpler, but the current flow capability and voltage withstand performance are limited
Solution Approach 1:
The patent segments the electrode configuration into multiple electrode groups positioned on different sides of the heterojunction. First electrodes are positioned on the upper side of the first heterojunction and second electrodes are positioned on the lower side, with each electrode group connected to separate conductor interconnection layers. This segmentation enables independent electrical contact with the vertical 2DEG channel from both directions, doubling the current flow pathways and significantly improving power handling capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-channel structure increases on-current and improves voltage withstand performance, while removing the substrate's influence, particularly heterogeneous substrates, leading to higher power and better heat resistance.
Implementation Method 1
a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction
Implementation Method 2
a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first channel layer; a first barrier layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode positioned on an upper side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the first electrode is connected to a first external voltage above the first heterojunction; and a second electrode positioned at a lower side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the second electrode is connected to a second external voltage below the first heterojunction. The semiconductor device of the present disclosure can not only improve the withstand voltage of the device, but also facilitate the circuit interconnection of the semiconductor device.