Vertical 2T Memory Cell Structure for Higher-Density Low-Power Arrays
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, limiting their ability to efficiently store information and manage power dissipation.
Innovation Solution
The development of a memory device with two-transistor (2T) memory cells, featuring a cross-point gain cell structure that allows for a smaller footprint, reduced power consumption, and improved read and write channel regions, utilizing a single access line and data line for operations, and multiple levels of memory cells stacked on each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional capacitor-based memory cells are used, then information storage function is achieved, but memory cell size cannot be reduced further due to physical limitations and fabrication constraints
Solution Approach 1:
The patent transitions from planar 1T1C memory cell architecture to a vertical 2T memory cell architecture where transistors are stacked in the vertical dimension. This allows the memory cell footprint to be reduced while maintaining functionality, as the transistor channels extend vertically rather than horizontally, overcoming the area scaling limitations of conventional approaches.
Solution Approach 2:
The patent changes the architectural parameters from single-transistor capacitor-based storage to dual-transistor vertical channel structure with charge trapping layer. This parameter change enables smaller cell size while improving fabrication robustness through the use of charge trapping layers that are less sensitive to dimensional variations.
2Quantity of substance
If memory cell size is reduced to increase storage density, then device storage density increases, but physical limitations and fabrication constraints are exceeded
Solution Approach 1:
By stacking transistors vertically and using vertical channel structures, the patent achieves higher storage density without requiring proportionally smaller feature sizes. The vertical dimension provides additional space for transistor channels and charge storage regions, allowing density improvement while maintaining manufacturable lateral dimensions.
Solution Approach 2:
The patent employs composite material structures including charge trapping layers combined with semiconductor layers, and multi-layer gate structures. These composite materials enable precise charge control and robust fabrication processes, allowing high storage density to be achieved while maintaining manufacturing precision through material properties rather than solely relying on dimensional scaling.
3Loss of energy
If conventional memory cell architecture is used, then information storage is achieved, but power dissipation is not efficiently managed
Solution Approach 1:
The patent extracts the charge storage function from the transistor gate oxide and places it in a dedicated charge trapping layer. This separation allows the transistor to be turned off more completely, reducing leakage current and power dissipation, while the charge trapping layer retains information without requiring continuous power.
Solution Approach 2:
The charge trapping layer provides self-service by automatically trapping and holding charges without requiring external power or refresh operations. The trapped charges naturally remain stable due to the trapping mechanism, eliminating the need for continuous power supply to maintain stored information, thus reducing power dissipation.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.