Vertical 2T Memory Cell Structure for Higher Density and Lower Power
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, leading to inefficiencies in power dissipation and operation complexity.
Innovation Solution
A memory device with 2-transistor (2T) volatile memory cells, featuring a charge storage structure and a cross-point gain cell structure, uses a single access line to control two transistors, allowing for a smaller footprint and improved processing efficiency, with reduced power consumption and simplified operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell designs are used to increase storage density, then storage density improves, but physical limitations and fabrication constraints worsen
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical structure where the charge storage structure extends vertically with multiple channels accessing it from different levels. This dimensional change allows increased storage density without proportionally reducing cell footprint, as the storage capacity scales with vertical height rather than horizontal area alone.
Solution Approach 2:
The memory cell is segmented into distinct functional components: multiple channel structures (first and second channels) that are spatially separated but vertically aligned to access the same charge storage structure. This segmentation allows independent control and optimization of each channel while sharing the storage element, improving manufacturability.
2Quantity of substance
If memory cell size is reduced to increase storage density, then storage density improves, but power dissipation worsens
Solution Approach 1:
Multiple channel structures are merged to share a single charge storage structure, meaning that the storage function is consolidated while the access paths are distributed. This reduces redundant storage elements and associated power consumption, as the same storage node serves multiple channels, thereby reducing overall power dissipation for a given storage capacity.
3Reliability
If conventional memory cell designs are used, then operational reliability is maintained, but device complexity increases
Solution Approach 1:
The charge storage structure serves multiple functions simultaneously: it is accessed by the first channel for one type of operation and by the second channel for another operation, effectively making it a multi-functional element. This universality reduces the need for separate dedicated storage elements for different operations, simplifying the overall device structure while maintaining operational reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2T memory cell design achieves a smaller footprint, lower power dissipation, and more reliable read/write channels, enhancing storage density and operational simplicity compared to conventional designs.
Implementation Method 1
One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.