Vertical 2T0C DRAM Cell Structure for High-Density Low-Leakage Memory
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Solution Overview
Problem
The integration level of two-dimensional or planar semiconductor devices is limited by the cost of advanced equipment needed for fine pattern formation, and existing 3D DRAM cells face challenges with storage capacitors, hindering scalability.
Innovation Solution
A 2T0C type DRAM cell structure with vertically stacked transistors and a capacitor-less design, featuring a first and second transistor layer with a gate dielectric layer, and a preparation method that includes stacking electrode and sacrificial layers, etching, and filling with dielectric material to form a stable and high-integration semiconductor memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are used to overcome integration limitations, then integration level is improved, but storage capacitors are required which limit scalability
Solution Approach 1:
The patent extracts and eliminates the storage capacitor component from the memory cell structure, transitioning from a 1T1C (one transistor one capacitor) or 2T1C structure to a 2T0C (two transistors zero capacitors) structure. This removal of the capacitor component directly resolves the scalability limitation while maintaining high integration levels through vertical stacking of transistors only.
Solution Approach 2:
The patent implements vertical stacking of transistors in the third dimension, arranging multiple transistor layers (first transistor layer, second transistor layer, third transistor layer) vertically above each other. This dimensional transition from planar to vertical architecture enables higher integration density without requiring capacitors, as the vertical stacking itself provides the necessary isolation and functionality.
2Productivity
If vertical stack integration is implemented, then integration level is improved, but leakage current increases
Solution Approach 1:
The patent segments the vertical stack into distinct transistor layers (first, second, and third transistor layers) separated by isolation layers. Each transistor layer is independently controlled with its own gate electrodes, allowing precise control of current flow in each segment. This segmentation enables the vertical integration benefits while controlling leakage through independent gate control and isolation structures.
Solution Approach 2:
The patent introduces isolation layers as intermediary structures between the first, second, and third transistor layers. These isolation layers act as mediators that electrically isolate adjacent transistor layers, preventing unwanted current leakage between them while still allowing the vertical stacking architecture to provide high integration density.
3Ease of manufacture
If conventional preparation methods are used, then manufacturing process is simple, but mechanical stability and electrical stability of stack structure are insufficient
Solution Approach 1:
The patent employs composite material structures combining different semiconductor materials with distinct crystal orientations in the vertical stack. The first, second, and third transistor layers use different crystal orientations (e.g., <100>, <110>, <111>) which provides both mechanical strength through varied crystal structures and electrical stability through optimized carrier transport in each layer, while maintaining manufacturability through standard semiconductor processing.
Data Source
AI summary
The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.