Vertical 3D Memory Cell Layout for Reduced Footprint and Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As design rules shrink, semiconductor space for fabricating memory cells becomes limited, leading to challenges in reducing the footprint and mobility constraints, and increasing the operating voltage in conventional memory devices.
Innovation Solution
A three-dimensional memory design with vertically oriented access devices and horizontally oriented storage nodes, featuring a vertical channel and reduced footprint, which includes a stack of memory cells with access devices and storage nodes, allowing for increased access device width and reduced operating voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional memory cell design is used, then manufacturing process is simpler, but footprint area increases and access device width is limited
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell layout to a three-dimensional vertical stack configuration. Multiple memory cells are stacked vertically along a third dimension (z-axis), allowing increased storage density without increasing the lateral footprint area. The bit line extends in a first direction (x-axis) and word lines extend in a second direction (y-axis), with memory cells stacked in the third direction, creating a vertical channel structure that reduces the area occupied by each memory cell while maintaining access functionality.
2Speed
If access device width is increased, then mobility improves, but footprint area increases
Solution Approach 1:
The access device width is extended in the vertical direction (third dimension) through the stacked memory cell configuration. The vertical channel allows the access device to have greater effective width without increasing the lateral footprint area, thereby improving carrier mobility and access device performance while maintaining a compact footprint.
3Productivity
If design rules shrink, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
By stacking memory cells vertically in the third dimension, the patent achieves higher device density without requiring proportional shrinkage of lateral dimensions. This vertical integration approach reduces the demand for extreme manufacturing precision in the x-y plane, as density improvement is achieved through the z-axis stacking rather than lateral feature size reduction.
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source/drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source/drain region and horizontally oriented digit lines coupled to the second source/drain regions.