Vertical 3D Memory Device With Segmented Pillar Selection Layer
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Solution Overview
Problem
Current memory devices face challenges in increasing memory cell density, reducing power consumption, and improving access efficiency in three-dimensional vertical architectures while maintaining reliability and reducing manufacturing costs.
Innovation Solution
A vertical 3D memory device with an NMOS TFT selector, featuring a memory layer with a three-dimensional array of memory cells accessed through orthogonal word and digit lines, a pillar selection layer with thin film transistors, and a peripheral circuit layer with sense amplifiers and decoding circuitry, allowing for efficient selection and programming of individual memory cells using biasing voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical 3D memory architecture is used to increase memory cell density, then memory cell density is improved, but manufacturing complexity increases
Solution Approach 1:
The memory device is divided into distinct functional layers: a first substrate with memory cells, a second substrate with access transistors, and intermediate connection structures. This segmentation allows each layer to be optimized and manufactured separately, then stacked together, increasing memory cell density while managing manufacturing complexity through modular fabrication processes
Solution Approach 2:
The patent transitions from planar 2D memory architecture to vertical 3D architecture by stacking memory cells and access transistors on separate substrates in the vertical dimension. This dimensional change enables higher memory cell density without proportionally increasing the footprint area, while the modular layering approach helps manage manufacturing complexity
2Productivity
If more selection elements are added to improve access efficiency, then access efficiency is improved, but device complexity increases
Solution Approach 1:
The selection function is extracted from the memory cell layer and placed in a separate access transistor layer on the second substrate. Each access transistor independently controls access to its associated memory cell, improving access efficiency by enabling parallel operations while reducing device complexity through functional separation and modular design
3Use of energy by moving object
If three-dimensional vertical architecture is implemented to reduce power consumption, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The power consumption reduction is achieved through segmented architecture where memory cells on the first substrate and access transistors on the second substrate operate independently. This segmentation enables selective activation of only necessary components, reducing overall power consumption while the modular fabrication process manages manufacturing precision requirements through standardized interconnection techniques
Data Source
AI summary
The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.