Vertical Access Device With Localized Dielectric Thickness
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Solution Overview
Problem
Prior art vertical access devices in DRAM memory devices suffer from localized dielectric breakdown at corner regions due to high electrostatic potentials, which can be partially mitigated by increasing dielectric layer thickness, but this reduces gate capacitance and affects switching time.
Innovation Solution
The solution involves forming vertical access devices with a dielectric layer structure that includes a trench dielectric layer and a conductive film on the sidewalls and floor of the recess, where the conductive film is etched to create a lower edge extending into the trench, and doped regions are used to control conductivity, optimizing gate capacitance and reducing electrostatic stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the dielectric layer is increased to prevent dielectric breakdown at corner regions, then the reliability is improved, but the gate capacitance is reduced which adversely affects switching time
Solution Approach 1:
The patent applies different dielectric layer thicknesses to different regions of the memory device. Specifically, the first dielectric layer has a greater thickness at the corner regions compared to the center regions. This local variation allows the corner regions (which experience higher electrostatic stress) to have enhanced breakdown resistance, while the center regions maintain thinner dielectric layers that preserve gate capacitance and switching performance.
2Productivity
If the feature size of memory cell components is decreased to increase packing density, then the productivity is improved, but the electrostatic potential at corner regions increases leading to dielectric breakdown
Solution Approach 1:
The patent implements non-uniform dielectric layer thickness distribution where corner regions have increased thickness compared to center regions. This local enhancement provides targeted protection against dielectric breakdown at corner regions, enabling the use of smaller feature sizes and higher packing densities without sacrificing reliability at the vulnerable corner locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances packing density while minimizing dielectric breakdown and maintaining adequate switching performance by optimizing the dielectric and conductive film structure, thus improving the reliability and efficiency of DRAM memory devices.
Implementation Method 1
A dielectric layer is generally applied to an interior of the recess, and a selective doping is employed to impart a desired conductivity to the side wall regions.
Implementation Method 2
corner regions may generate relatively high electrostatic potentials that may lead to a localized dielectric breakdown in the corner region
Implementation Method 3
as the thickness of a selected dielectric layer is increased, a gate capacitance in the device is reduced, which may adversely affect switching time for the device
Data Source
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AI summary
Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess (50) in a semiconductor substrate (12) that includes a pair of opposed side walls (73, 75) and a floor (48) extending between the opposed side walls. A dielectric layer (62) may be deposited on the side walls and the floor of the recess. A conductive f ilm. (64) may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.