Vertical Access Line Multiplexor for 3D Memory Arrays
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Solution Overview
Problem
As design rules shrink, there is limited semiconductor space for fabricating memory devices, particularly for DRAM arrays, where existing technologies require individual access line drivers and connections, making it challenging to efficiently control and access vertically stacked memory cells in 3D memory systems.
Innovation Solution
The implementation of a vertical access line multiplexor using n-type metal oxide semiconductor (nMOS) transistors eliminates the need for individual access line drivers and connections by allowing individual vertical access lines to be activated and deactivated through a multiplexor, simplifying the fabrication process and reducing space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If individual access line drivers and connections are used for each vertical access line, then each access line can be independently controlled, but the device complexity and space requirements increase significantly
Solution Approach 1:
Multiple vertical access lines are merged into a single horizontal access line through a multiplexor located beneath the memory array. The multiplexor combines several vertical access lines (e.g., 4, 8, or 16 lines) into one horizontal access line, allowing independent control of each vertical line while sharing common control circuitry. This reduces the number of access line drivers from one per vertical line to one per group of vertical lines.
Solution Approach 2:
The horizontal access line serves multiple functions: it acts as a common control line for multiple vertical access lines, provides power to the multiplexor transistors, and enables selective activation of different vertical lines through the multiplexor switching mechanism. This multi-functionality reduces the overall number of dedicated control lines needed in the system.
2Ease of operation
If individual access line drivers are implemented for each vertical access line, then full control capability is achieved, but the semiconductor space available for fabricating memory cells is reduced
Solution Approach 1:
The multiplexor structure merges multiple vertical access line control functions into a single horizontal access line infrastructure. By locating the multiplexor beneath the memory array and using shared horizontal access lines, the design eliminates the need for separate access line drivers for each vertical line, thereby freeing up semiconductor space for additional memory cells or reduced cell density requirements.
Solution Approach 2:
The invention transitions from a planar arrangement where access line drivers would occupy lateral space to a vertical arrangement where the multiplexor is positioned beneath the memory array. The horizontal access lines extend in the lateral dimension while controlling vertical access lines that extend in the vertical dimension, effectively utilizing the third dimension to reduce lateral space requirements.
3Device complexity
If a multiplexor structure is used to share horizontal access lines among multiple vertical access lines, then space and complexity are reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The multiplexor transistors are formed using the same semiconductor fabrication processes as the memory cells themselves, utilizing the existing nMOS or pMOS transistor formation steps. The multiplexor transistors serve themselves by using the same material layers, doping processes, and gate formation techniques already employed for the memory array, thereby minimizing the need for additional or more precise manufacturing steps.
4Area of stationary object
If vertical access lines are coupled to horizontal access lines via multiplexors beneath the array, then space is optimized, but the energy required to activate and deactivate lines increases
Solution Approach 1:
The multiplexor transistors dynamically switch between connecting different vertical access lines to the shared horizontal access line based on the selected memory row. The transistors are activated only when needed to connect a specific vertical line, and deactivated otherwise, allowing the system to adapt its energy consumption to the actual access patterns rather than continuously powering all access lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables simplified fabrication and efficient operation of 3D memory devices by allowing for the activation and deactivation of vertical access lines, reducing the complexity and space needed for access line drivers, thereby improving the scalability and efficiency of 3D memory systems.
Implementation Method 1
The multiplexor can include a first transistor and a second transistor. The first transistor can have a first terminal coupled to the vertical access line and to a first terminal of the second transistor. The first transistor can have a second terminal coupled to the horizontal access line. The second transistor can have a second terminal coupled to a power supply. Deactivation of the first transistor and activation of the second transistor can cause the vertical access line to be coupled to the power supply. Activation of the first transistor and deactivation of the second transistor can cause the vertical access line to be coupled to the horizontal access line.
Data Source
AI summary
An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.