Vertical Access Devices With Segmented Pillars For DRAM Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device design is to achieve higher packing densities and minimize electrical coupling effects and pattern noise in vertical access devices, particularly for DRAM applications, where shrinking word line spacing leads to undesirable electrical coupling and increased pattern noise.
Innovation Solution
The solution involves forming vertical access devices with semiconductive pillars extending from a semiconductive base, where the pillars are separated by isolation structures and tailored dimensions and spacings are used to achieve high packing densities and improved electrical properties, including single-gate configurations with body contacts to suppress floating body effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word line spacing is shrunk to increase packing density, then packing density is improved, but electrical coupling effects and pattern noise increase
Solution Approach 1:
The semiconductor pillar is divided into multiple channel regions separated by non-conductive spacer regions. This segmentation electrically isolates adjacent channel regions, reducing electrical coupling effects between closely spaced word lines while maintaining high packing density. The non-conductive spacer regions act as barriers that prevent harmful electrical interactions.
Solution Approach 2:
Non-conductive spacer regions are introduced as intermediary elements between adjacent channel regions. These spacers serve as mediators that electrically isolate the channel regions while allowing the structure to maintain compact dimensions. The intermediary spacers prevent direct electrical coupling between adjacent word lines.
2Quantity of substance
If vertical access devices are used to increase packing density, then packing density is improved, but manufacturing complexity increases
Solution Approach 1:
The formation process segments the manufacturing into distinct stages: forming the semiconductor pillar, depositing conformal layers, and selectively removing portions. This segmented approach simplifies manufacturing by breaking down the complex vertical device formation into manageable steps that can be integrated into existing fabrication processes.
Solution Approach 2:
The invention transitions from planar device geometry to vertical device geometry, utilizing the third dimension (vertical extent) to increase packing density. By forming channel regions that extend vertically through the semiconductor pillar, the device achieves higher density without proportionally increasing manufacturing complexity, as the vertical structure can be formed using standard deposition and etching techniques.
3Reliability
If non-conductive spacer regions are added to reduce electrical coupling, then electrical properties are improved, but device structure complexity increases
Solution Approach 1:
The non-conductive spacer regions are merged with the semiconductor pillar to form an integrated structure. The spacers are not separate components but are formed as part of the pillar fabrication process through conformal deposition and selective removal. This merging reduces overall device structure complexity while maintaining the electrical isolation benefits.
Solution Approach 2:
The non-conductive spacer regions serve multiple functions: they electrically isolate adjacent channel regions, define the boundaries of conductive regions during formation, and maintain structural integrity of the semiconductor pillar. This multi-functionality reduces the need for additional specialized structures, thereby simplifying the overall device design.
Data Source
AI summary
A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.