Vertical Access Transistors for DRAM Refresh and Row Hammer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM memory arrays with planar access transistors face challenges in refresh performance and are susceptible to row hammer effects, which affect data retention and memory cell stability.
Innovation Solution
The use of vertical thin-film transistors (TFTs) positioned between local digit lines and hierarchical digit lines reduces space requirements, allows for improved refresh performance, and minimizes row hammer effects by enabling a hierarchical digit line structure that amplifies signals effectively and reduces signal weakening over distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar access transistors are used in conventional DRAM memory arrays, then the memory array can be manufactured with established processes, but the refresh performance deteriorates and row hammer effects occur
Solution Approach 1:
The patent transitions from planar (2D) access transistors to vertical (3D) access transistors, changing the dimensional configuration of the transistor structure. This vertical configuration allows the transistor channel to extend in the vertical direction rather than lying flat in the plane, thereby improving refresh performance while managing structural complexity through a different spatial arrangement.
2Reliability
If planar access transistors are used, then the transistor layout is simple, but the memory array is susceptible to row hammer effects and has poor data retention
Solution Approach 1:
By changing from planar to vertical transistor configuration, the patent alters the spatial relationship between memory cells and access transistors. This vertical arrangement modifies the electrical field distribution and access patterns, thereby reducing susceptibility to row hammer effects and improving data retention through better charge isolation and control.
3Reliability
If vertical access TFTs are implemented, then refresh performance improves and row hammer effects are reduced, but the transistor structure becomes more complex
Solution Approach 1:
The vertical TFT structure is segmented into distinct functional regions including the vertical channel, gate electrodes positioned at different heights, source and drain regions, and insulating layers. This segmentation allows each component to be optimized independently for its specific function while maintaining overall structural integrity and managing manufacturing complexity through modular design.
Solution Approach 2:
The patent employs vertical stacking of transistor components in the third dimension, with gate electrodes positioned at different vertical levels and the channel extending vertically. This dimensional change enables improved memory cell stability through better charge control and isolation, while the compact vertical footprint helps manage overall device complexity by reducing lateral space requirements.
4Area of stationary object
If vertical access TFTs are used, then the memory array becomes more compact, but the manufacturing process becomes more difficult
Solution Approach 1:
The vertical TFT configuration consolidates multiple transistor components into a compact vertical stack, significantly reducing the lateral footprint of each memory cell. This vertical integration achieves higher density while the manufacturing process manages complexity through sequential deposition and patterning steps that build the vertical structure layer by layer, making the complex geometry achievable with adapted standard semiconductor fabrication techniques.
Data Source
AI summary
An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.