Vertical Active Pattern Layout for Contact-Gate Short Isolation
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Solution Overview
Problem
The reduction in size of semiconductor device components leads to deteriorated dispersion characteristics, and existing technologies struggle to maintain reliability and prevent electrical shorts between contact plugs and gate electrodes.
Innovation Solution
A semiconductor device design incorporating a vertical active pattern with bend portions, an etch stop layer, and a dielectric layer to separate contact plugs from gate electrodes, ensuring a consistent distance and preventing electrical shorts, thereby improving scattering characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor device components is reduced, then the device size is decreased, but the dispersion characteristics deteriorate
Solution Approach 1:
The active pattern is designed with a vertical active portion extending in the vertical direction, transitioning from planar to three-dimensional structure. This vertical extension increases the effective channel length without increasing the planar footprint, allowing device scaling while maintaining electrical characteristics and reducing dispersion.
Solution Approach 2:
The active pattern includes bend portions that curve from the vertical active portion, creating a non-linear, curved path for charge carrier transport. This curved geometry optimizes the electrical characteristics by controlling the electric field distribution and carrier movement, improving device performance while maintaining compact dimensions.
2Volume of moving object
If contact plugs are positioned closer to gate electrodes to reduce device size, then the device size is decreased, but electrical shorts occur between contact plugs and gate electrodes
Solution Approach 1:
An etch stop layer is introduced as an intermediary barrier layer positioned between the contact plug and the gate electrode. This etch stop layer acts as a physical and electrical barrier, preventing direct contact and electrical shorts between the conductive contact plug and gate electrode, while allowing the etching process to proceed with proper depth control.
Solution Approach 2:
The etch stop layer is selectively positioned only in the critical region where the contact plug approaches the gate electrode, providing localized electrical isolation where needed. This local application maintains device miniaturization while preventing electrical shorts only in the necessary areas.
3Reliability
If the vertical active portion is extended to improve scattering characteristics, then the scattering characteristics are improved, but the device complexity increases
Solution Approach 1:
The vertical active portion, bend portions, and channel formation are merged into a single integrated active pattern structure. This unified structure achieves improved scattering characteristics through its three-dimensional geometry without requiring separate components or complex assembly, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes an active pattern having a vertical active portion extending in a vertical direction and a first bend portion bent from an upper region of the vertical active portion; a gate electrode spaced apart from the active pattern, wherein at least a portion thereof faces the vertical active portion; an etch stop layer in which at least a portion thereof is disposed between an upper surface of the gate electrode and the first bend portion; a dielectric layer in which at least a portion thereof is disposed between the active pattern and the gate electrode; and a contact plug disposed on the etch stop layer and at least penetrating through the first bend portion.