Vertical Anti-Fuse Stacking for Semiconductor Area Reduction
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Solution Overview
Problem
Conventional fuse elements in semiconductor devices occupy significant horizontal space, posing a challenge as semiconductor devices become more integrated and require a novel structure to address the space constraints.
Innovation Solution
A semiconductor structure featuring a first anti-fuse structure, a second anti-fuse structure stacked vertically over the first, and a metal layer between them, comprising specific layers such as a semiconductor substrate, dielectric layers, conductive layers, and electrodes, which allows for vertical arrangement reducing horizontal space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional fuse elements are arranged horizontally on the same surface, then the device structure is simple and easy to manufacture, but the horizontal area occupied is large
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking of anti-fuse structures. Multiple anti-fuse structures are arranged in different layers along the vertical direction, with lower-layer structures connected to first contact plugs and upper-layer structures connected to second contact plugs. This dimensional change dramatically reduces the horizontal area occupied by fuse elements while maintaining device functionality.
Solution Approach 2:
The patent divides the anti-fuse structures into multiple independent layers (lower-layer and upper-layer anti-fuse structures). Each layer can be independently formed, contacted, and controlled through separate contact plugs. This segmentation allows for reduced horizontal footprint while providing flexibility in circuit design and defect repair strategies.
2Adaptability or versatility
If more anti-fuse structures are integrated to repair defective circuits, then the repair capability increases, but the horizontal space required increases
Solution Approach 1:
By stacking anti-fuse structures vertically across multiple layers, the patent enables integration of multiple redundancy circuits without increasing horizontal space. The lower-layer anti-fuse structures can repair defects in first circuit regions, while upper-layer structures can repair defects in second circuit regions, all within the same horizontal footprint.
Solution Approach 2:
The patent implements a hierarchical nesting arrangement where upper-layer anti-fuse structures are positioned above and can repair defects in lower-layer circuit regions. This nested configuration allows multiple levels of redundancy to be packed into the same horizontal area, maximizing repair capability while minimizing space consumption.
Data Source
AI summary
A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.