Anti-Fuse Memory Structure With Vertical Cell Stacking for OTP Density

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Solution Overview

Problem

One-time programmable (OTP) memory devices face challenges such as large storage area, low integration, complex manufacturing processes, and high manufacturing costs due to their reliance on dynamic random access memory (DRAM) structures, which include selective transistors and breakdownable capacitors.

Innovation Solution

A semiconductor structure featuring a substrate with a gate structure and an anti-fuse bit structure, where the anti-fuse bit structure is located in a second layer connected to the substrate through a first connecting structure, allowing breakdown and non-breakdown states to represent different stored data, thereby reducing the memory cell size and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If OTP memory adopts a structure similar to DRAM, then data storage capability is achieved, but storage area increases and integration decreases

Engineering Contradiction:
Improvedata storage capabilityVSAvoidstorage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar DRAM-like structure to a three-dimensional stacked structure where the anti-fuse bit structure is positioned vertically above the selective transistor. This vertical stacking reduces the horizontal footprint of each memory cell, directly addressing the contradiction between maintaining data storage capability and reducing storage area for improved integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If OTP memory uses a DRAM-like structure, then data storage is enabled, but manufacturing process complexity increases

Engineering Contradiction:
Improvedata storageVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory cell into distinct functional layers: the selective transistor in the first structure layer and the anti-fuse bit structure in the second structure layer. This segmentation allows each component to be optimized and manufactured independently, simplifying the overall manufacturing process compared to the integrated DRAM-like structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate structure serves multiple functions: it acts as the gate electrode for the selective transistor and simultaneously functions as one of the electrodes for the anti-fuse bit structure. This multi-functionality reduces the total number of components and manufacturing steps, directly addressing the manufacturing complexity issue.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Quantity of substance

If additional horizontal space is allocated for anti-fuse bit structure, then data storage capacity is maintained, but memory integration is reduced

Engineering Contradiction:
Improvedata storage capacityVSAvoidmemory integration
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent utilizes the vertical dimension by stacking the anti-fuse bit structure above the selective transistor rather than placing it horizontally adjacent. This three-dimensional arrangement maintains the necessary components for data storage capacity while significantly reducing the horizontal area occupied by each memory cell, thereby improving memory integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances memory integration, reduces manufacturing complexity and costs, and stabilizes programming voltage, improving the reliability and efficiency of OTP memory devices.

Implementation Method 1

a breakdown state and a non-breakdown state of the anti-fuse bit structure represent different stored data

Methodology Applied
Scientific EffectDielectric breakdown: Avalanche Breakdown

Data Source

PatentUS20230422492A1Semiconductor structure and method for manufacturing same, memory and operation method thereof
Publication Date: 2023.12.28 CHANGXIN MEMORY TECH INC
  • US20230422492A1 patent drawing
  • US20230422492A1 patent drawing
  • US20230422492A1 patent drawing

AI summary

Provided is a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same. The semiconductor includes a substrate having a plurality of active areas close to a surface of the substrate; a gate structure located in a first structure layer on the substrate, in which the gate structure and the active areas constitute a selective transistor; and an anti-fuse bit structure located in a second structure layer on the first structure layer, and connected with an active area of one selective transistor through a first connecting structure, in which a breakdown state and a non-breakdown state of the anti-fuse bit structure represent different stored data.