Vertical Antifuse Co-Integrated with FinFET CMOS
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Solution Overview
Problem
Conventional planar anti-fuses have high breakdown voltage and occupy excessive area in advanced technology nodes, making them unsuitable for integration with vertical FinFET CMOS transistors, which is necessary for minimizing process costs and improving system integration in semiconductor applications.
Innovation Solution
A method for manufacturing vertical transistors co-integrated with anti-fuses, featuring a triangularly shaped anti-fuse structure with epitaxial growth, which enhances breakthrough voltage and current characteristics, using the same integration method as current FinFET CMOS structures to achieve high integrability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar anti-fuses are used, then they provide basic anti-fuse functionality, but they occupy excessive area and have too high breakdown voltage for advanced technology nodes
Solution Approach 1:
The patent transitions from planar anti-fuse structures to vertically stacked three-dimensional structures. The anti-fuse is formed as a vertical stack extending through multiple layers, including source, channel, drain, and gate regions arranged in the vertical dimension. This dimensional change reduces the lateral footprint while enabling better control over breakdown characteristics through the vertical architecture.
Solution Approach 2:
The patent modifies the breakdown voltage parameter by changing the structural configuration from planar to vertical stacked. The vertical architecture with controlled channel width and gate coverage ratio enables tuning of the breakdown voltage to appropriate levels for advanced technology nodes, resolving the issue of excessively high breakdown voltage in conventional planar designs.
2Reliability
If conventional planar anti-fuses are used, then they provide basic anti-fuse functionality, but their breakdown voltage is too high for integration with vertical FinFET CMOS transistors
Solution Approach 1:
The patent creates a universal vertical stacked structure that can serve both as a FinFET CMOS transistor and as an anti-fuse device. The same vertical architecture with source, channel, drain, and gate regions can be configured to achieve either transistor operation or anti-fuse breakdown characteristics, enabling single-patterning integration without requiring separate process streams.
Solution Approach 2:
The patent merges the anti-fuse structure with the vertical FinFET CMOS transistor fabrication process. Both devices share common structural elements including the vertical stacking approach, epitaxial growth methods, and doping techniques. This consolidation enables co-integration on the same chip using unified process steps.
3Ease of manufacture
If vertical stacked FinFET CMOS transistors are fabricated, then process cost is minimized and system integration is improved, but conventional planar anti-fuses cannot be integrated due to area and voltage mismatches
Solution Approach 1:
The vertical stacked structure serves dual purposes as both FinFET CMOS transistor and anti-fuse device, eliminating the need for separate planar anti-fuse fabrication processes. This universality maintains the cost benefits of single-patterning vertical fabrication while enabling anti-fuse functionality to be integrated alongside transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in anti-fuse structures with reduced breakdown voltage and improved integration with vertical transistors, addressing the area and voltage challenges of conventional anti-fuses, and enabling efficient system integration in current technology nodes.
Implementation Method 1
forming a channel region extending over the highly doped source and comprising an epitaxial growth, the channel region located at a first location on the substrate and having a first width. The method further includes forming a drain comprising an epitaxial growth arranged on the channel region
Data Source
AI summary
A semiconductor device comprising an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.