Vertically Stacked Anti-Fuse Cell for FinFET Reliability Margin
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Solution Overview
Problem
The reliability and operation margin of traditional anti-fuses in semiconductor ICs are compromised due to scaling down of transistors, particularly in FinFET and gate-all-around devices, and are affected by changes in front-end and middle-end of line processes.
Innovation Solution
A new type of anti-fuse is implemented at metal layers above transistors, featuring vertically stacked fuse elements with metal plates as terminals, allowing for higher read current and improved reliability through decoupling of transistor and fuse tuning, and providing two parallelly connected fuse elements for enhanced programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional anti-fuse structures are used with scaled-down transistors, then device density increases, but reliability and operation margin deteriorate
Solution Approach 1:
The patent transitions from planar anti-fuse structures to vertically stacked three-dimensional structures. Multiple fuse elements are stacked in the vertical dimension above the transistor, allowing increased device density while maintaining adequate breakdown voltage and operation margin for each individual fuse element. This vertical stacking enables the system to achieve high density without compromising reliability.
Solution Approach 2:
The anti-fuse structure is segmented into multiple independent fuse elements stacked vertically. Each fuse element can be independently controlled and broken down, allowing the system to achieve higher density while maintaining adequate operation margin for each segment. The segmentation also enables selective programming of individual fuse elements.
2Productivity
If transistor geometry is scaled down to increase functional density, then production efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The vertically stacked fuse elements share common transistor structures and control mechanisms. Multiple fuse elements can be programmed and controlled using the same transistor layer and control circuitry, reducing the need for additional specialized components and processes. This multi-functionality approach maintains manufacturing efficiency while achieving high density.
3Device complexity
If anti-fuse breakdown path is through transistor gate to channel or drain, then structure simplicity is maintained, but resistance variation and operation margin worsen
Solution Approach 1:
The fuse elements are extracted from the transistor structure and placed in separate metal layers above the transistor. This separation allows the fuse elements to have dedicated metal plates as terminals rather than relying on transistor gate/channel/drain structures. The extraction provides better control over fuse characteristics and reduces resistance variation while maintaining structural simplicity through modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new anti-fuse design enhances reliability and programmability with lower resistance between metal terminals, offering higher read current and flexibility in programming voltage, addressing the limitations of traditional anti-fuses in scaled-down transistor designs.
Implementation Method 1
Once the insulator breaks down, the fuse element is programmed. After being programmed, the resistance between the two metal plates becomes very small
Data Source
AI summary
A semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. The semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. The first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. The second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. The source terminal of the first transistor is electrically connected to the first metal plate. The source terminal of the second transistor is electrically connected to the third metal plate. The program line is electrically connected to the second metal plate.