Vertical Barrier Design for 3D Semiconductor Memory Stability
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face structural instability issues as the number of stacked memory cells increases, affecting the degree of integration and reliability.
Innovation Solution
A semiconductor memory device is designed with a dummy stack structure and a cell stack structure surrounded by a vertical barrier, where the vertical barrier has different sectional areas on either side of the boundary between the two stack structures, enhancing structural stability and manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacking number of memory cells is increased to improve the degree of integration, then the integration density is improved, but structural stability deteriorates
Solution Approach 1:
The stack structure is divided into multiple segments with dummy stacks inserted between cell stacks. This segmentation reduces the continuous height of conductive materials, preventing structural instability while maintaining high integration density through increased stacking numbers.
Solution Approach 2:
Dummy stack structures are introduced as intermediary elements between cell stacks. These dummy stacks act as mediators that break the continuity of conductive materials, preventing structural instability caused by excessive stacking while allowing the overall integration density to increase.
2Ease of manufacture
If a vertical barrier with uniform sectional area is used, then the manufacturing process is simple, but conductive material intrusion occurs between stack structures
Solution Approach 1:
The vertical barrier is designed with non-uniform sectional area, where the width varies at different heights. The barrier is wider at the lower portion to prevent conductive material intrusion, and narrower at the upper portion for manufacturing ease. This local variation in geometry provides enhanced protection where needed while maintaining manufacturing simplicity.
Solution Approach 2:
The vertical barrier exhibits asymmetric geometry with different widths at different heights. This asymmetric design allows the barrier to effectively block conductive material intrusion at critical lower regions while maintaining manufacturing simplicity in the upper regions, resolving the contradiction between prevention effectiveness and manufacturing ease.
Data Source
AI summary
A semiconductor memory device includes a dummy stack structure having a first stack structure and a second stack structure formed on the first stack structure. The semiconductor memory device also includes a cell stack structure surrounding the dummy stack structure. The semiconductor memory device further includes a vertical barrier disposed at a boundary between the cell stack structure and the dummy stack structure, the vertical barrier including a first part formed on a sidewall of the first stack structure and a second part formed on a sidewall of the second stack structure. A sectional area of the first part of the vertical barrier is greater than a sectional area of the second part of the vertical barrier at a height at which a boundary between the first stack structure and the second stack structure is disposed.