Vertical BEOL Transistor Structure for Dense Memory Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Front-end-of-line (FEOL) transistors pose a bottleneck in achieving higher density non-volatile memories, requiring larger transistors or multiple transistors in parallel to support high write currents, which leads to a significant area penalty, while back-end-of-line (BEOL) transistors face reliability issues due to damage from the damascene process during via formation.
Innovation Solution
A BEOL transistor design with a vertically stacked source and drain electrode configuration, using a dielectric spacer to protect the oxide semiconductor layer, and integrating memory cells within the metal interconnect structure, avoiding the damaging etch process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FEOL transistors are used to support high write currents, then the drive current capability is improved, but the area occupied by the transistor increases significantly
Solution Approach 1:
The transistor structure transitions from a planar configuration to a vertical three-dimensional configuration. The source and drain electrodes are stacked vertically with the channel extending in the vertical dimension, allowing high current capability without increasing the lateral footprint area.
Solution Approach 2:
The channel is formed within the vertical structure by coating the sidewall of the dielectric spacer, creating a nested configuration where the conductive path is contained within the vertical stack of electrodes and insulating layers.
2Ease of manufacture
If the damascene process is used to form vias in BEOL transistors, then the via formation is achieved, but the oxide semiconductor layer is damaged
Solution Approach 1:
The source and drain electrodes are formed as complete vertical stacks before the via formation process. The dielectric spacer is already in place protecting the oxide semiconductor channel, so subsequent via etching does not expose or damage the semiconductor layer.
Solution Approach 2:
The dielectric spacer acts as a protective intermediary layer between the source/drain electrodes and the oxide semiconductor channel. It shields the channel from the damaging effects of the damascene etch process while allowing the electrodes to be properly formed.
3Power
If larger transistors or multiple transistors are used in parallel, then the write current capability is improved, but the area penalty increases
Solution Approach 1:
The invention moves the current-carrying structure into the vertical dimension by stacking source and drain electrodes with a vertically extending channel. This three-dimensional configuration provides high current capability without increasing the lateral device area.
Solution Approach 2:
The transistor employs a composite structure combining oxide semiconductor channel material with vertically stacked conductive electrode layers and dielectric spacer materials, creating an integrated high-current-density device.
Data Source
AI summary
A back-end-of-line (BEOL) transistor includes a source electrode vertically stacked over a drain electrode and spaced apart from the drain electrode by a dielectric spacer between the first and second horizontal conductive layers. A semiconductor layer extends vertically between the source electrode and the drain electrode along a sidewall of the dielectric spacer. The drain electrode provides a channel for the transistor. A gate dielectric layer and a gate electrode are disposed over the gate dielectric layer. This structure allows the transistor to be manufactured without an etch process that can introduce defects into the semiconductor layer. The source electrode may be extended laterally to provide the bottom electrode of a memory cell that is integrated with the BEOL transistor.