Vertical Bipolar Transistor with All-Around Base
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Solution Overview
Problem
Current bipolar junction transistor fabrication techniques face challenges in achieving small base-collector capacitance and symmetry in emitter/collector configurations, particularly when using silicon substrates, due to lattice mismatch and threading dislocations.
Innovation Solution
The method involves epitaxial growth of III-V compound semiconductor layers within trenches on a silicon substrate, using aspect ratio trapping to reduce dislocation density, and forming a vertical column structure with a doped extrinsic base surrounding a III-V compound semiconductor sublayer, along with sacrificial layers and chemical mechanical planarization to create a symmetrical bipolar junction transistor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bipolar junction transistor fabrication techniques are used on silicon substrates, then manufacturing simplicity is maintained, but base-collector capacitance cannot be reduced sufficiently and emitter/collector symmetry is compromised due to lattice mismatch and threading dislocations
Solution Approach 1:
The device is segmented into distinct functional regions: a vertical column containing emitter, base, and collector regions, surrounded by an annular base region. This segmentation allows the inner vertical column and outer annular base to be independently optimized, enabling reduced base-collector capacitance through the vertical column geometry while maintaining manufacturability through standardized epitaxial growth processes for each segment
Solution Approach 2:
The invention transitions from a planar transistor layout to a vertical three-dimensional structure. The vertical column extends in the depth dimension with emitter, base, and collector regions stacked vertically, while the annular base extends in the radial dimension. This dimensional transformation reduces the horizontal base-collector junction area, thereby reducing base-collector capacitance while maintaining a fabrication process compatible with silicon substrates
2Reliability
If asymmetric emitter/collector configurations are used to simplify fabrication, then manufacturing ease is improved, but device performance is compromised; conversely, achieving symmetry increases fabrication complexity
Solution Approach 1:
The invention employs intentional asymmetry in the vertical column design where the emitter and collector regions have different doping concentrations and geometries optimized for their respective functions, while the annular base provides a symmetric surrounding structure. This controlled asymmetry within an otherwise symmetric annular configuration allows independent optimization of emitter and collector performance while maintaining overall device symmetry through the circular annular base geometry
Solution Approach 2:
Different regions of the device are assigned different material compositions and doping characteristics tailored to their specific functional requirements. The vertical column contains heavily doped emitter and collector regions with specific III-V compound semiconductor materials, while the annular base has optimized doping profiles for carrier injection. This local quality differentiation enables asymmetric emitter/collector optimization without compromising overall device symmetry or increasing global fabrication complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a bipolar junction transistor with reduced base-collector capacitance and symmetrical emitter/collector configurations, facilitating fabrication on silicon substrates and improving device performance.
Implementation Method 1
A vertical column of III-V compound semiconductor material is formed within the vertically extending trench by epitaxially growing a III-V compound semiconductor buffer layer on the substrate
Implementation Method 2
epitaxially growing a heavily doped III-V compound semiconductor bottom sublayer having a first conductivity type on the buffer layer, epitaxially growing a doped III-V compound semiconductor middle sublayer having a second conductivity type opposite to the first conductivity type on the bottom sublayer; and epitaxially growing a heavily doped III-V compound semiconductor top sublayer having the first conductivity type on the middle sublayer
Data Source
AI summary
A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Aspect ratio trapping is employed during fabrication of the transistor device on a silicon substrate. Homojunction and heterojunction devices are formed using III-V materials with appropriate bandgaps. The emitter of the device may be electrically connected by a lateral buried metal contact.