Vertical Bit Line Structures in 3D Nonvolatile Memory
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Solution Overview
Problem
As semiconductor memory devices are scaled down to reduce cost per bit, design and process challenges arise, particularly in monolithic three-dimensional non-volatile memory arrays where leakage currents are significant due to the absence of isolation elements between memory cells, affecting the efficiency and reliability of memory operations.
Innovation Solution
The implementation of a monolithic three-dimensional memory array with vertical bit lines and bit line select devices, such as gated resistors or junctionless transistors, is used to reduce leakage currents by isolating local bit lines and associating each bit line select transistor with multiple local bit lines, thereby controlling the voltage applied to global bit lines and optimizing memory cell selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory devices are scaled down to reduce cost per bit, then manufacturing cost decreases, but leakage currents increase significantly
Solution Approach 1:
The bit line is divided into multiple local bit lines, each independently controlled by its own bit line select transistor. This segmentation allows individual control of current flow to each local bit line, preventing leakage currents from affecting the entire bit line and enabling selective activation only when needed.
Solution Approach 2:
Bit line select transistors are introduced as intermediary devices between the global bit line and local bit lines. These transistors act as controlled switches that mediate current flow, allowing precise control over which local bit lines are activated and preventing unwanted leakage currents from propagating through the memory array.
2Object-generated harmful factors
If isolation elements are added between memory cells to reduce leakage currents, then leakage control improves, but device complexity increases
Solution Approach 1:
The bit line select transistors serve multiple functions: they act as isolation elements to prevent leakage currents, serve as selection mechanisms for accessing specific memory cells, and function as control switches for activating local bit lines. This multi-functionality eliminates the need for separate isolation elements, reducing overall device complexity while maintaining leakage control.
3Quantity of substance
If vertical bit line structures are implemented in three-dimensional memory arrays, then memory density increases, but control over voltage application becomes more challenging
Solution Approach 1:
The vertical bit line structure is segmented into multiple local bit lines, each associated with specific memory cell layers. This segmentation enables selective voltage application to targeted regions of the three-dimensional memory array, simplifying control by limiting voltage changes to only the necessary local areas rather than the entire vertical structure.
Solution Approach 2:
Bit line select transistors serve as intermediary control devices between control circuitry and vertical bit lines. These transistors provide localized voltage control at the intersection of bit lines and word lines, enabling precise addressing of specific memory cells in the three-dimensional array without requiring complex global voltage management.
Data Source
AI summary
A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.