Vertical Bit Vector Shift in Memory Using Embedded Sensing Circuitry
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Solution Overview
Problem
Existing memory technologies face inefficiencies in performing vertical bit vector shifts, requiring significant computational time and power consumption due to the need for data transfer between memory arrays and processing resources via buses, which limits processing performance and increases energy usage.
Innovation Solution
The implementation of sensing circuitry within the memory array allows for the performance of vertical bit vector shifts directly within the memory, eliminating the need for data transfer via buses by using local operations, thereby reducing computational time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between memory arrays and processing resources via buses to perform vertical bit vector shifts, then processing can be performed, but computational time and power consumption increase significantly
Solution Approach 1:
The patent merges the memory array and processing resources into a single integrated structure where processing units are embedded within the memory array. This allows vertical bit vector shifts to be performed directly within the memory array using local operations, eliminating the need for data transfer via external buses and thereby reducing both computational time and power consumption.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components within the memory array that enable local data manipulation and processing. These sense amplifiers facilitate vertical bit vector shift operations by providing intermediate storage and processing capability within the memory array itself, avoiding the need to transfer data to external processing resources.
2Productivity
If data is transferred via buses between memory and processing resources, then operations can be executed, but processing performance is limited
Solution Approach 1:
The patent combines memory storage and processing functions into a single integrated memory array structure. Processing units are embedded within the memory array, enabling operations such as vertical bit vector shifts to be performed in-place without data transfer delays. This integration dramatically improves processing performance and eliminates the time loss associated with bus transfers.
Solution Approach 2:
The patent performs preliminary processing actions directly within the memory array before data needs to be transferred to external processing resources. By executing vertical bit vector shift operations and other preprocessing tasks within the memory array using embedded processing units, the system prepares data in advance, reducing the amount of data that needs to be transferred and the time required for subsequent processing.
3Ease of operation
If data transfer via buses is used for vertical bit vector shifts, then processing can be performed, but energy usage increases
Solution Approach 1:
The patent merges memory and processing functions into an integrated structure where vertical bit vector shift operations are performed within the memory array using embedded processing units. This eliminates the need for energy-consuming data transfers via external buses while maintaining operational simplicity through a unified memory-processing architecture.
Solution Approach 2:
The patent enables the memory array to perform processing operations on its own stored data without requiring external processing resources. The embedded processing units within the memory array execute vertical bit vector shift operations using local data, making the system self-sufficient and eliminating the energy consumption associated with data transfer to and from external processors.
Data Source
AI summary
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.