Vertical Memory Bit-Line Structure for Higher Storage Density
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Solution Overview
Problem
Existing semiconductor devices face limitations in increasing data storage capacity, particularly in efficiently arranging memory cells to maximize storage density.
Innovation Solution
The semiconductor device incorporates a vertical channel structure with a plurality of gate electrodes and bit lines arranged in multiple layers, featuring inclined lower bit lines and parallel upper bit lines to enhance data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional to three-dimensional memory cell arrangement by introducing vertical channel structures that extend through multiple gate electrode layers. This dimensional change enables increased storage capacity by utilizing the vertical space above the substrate, allowing memory cells to be stacked in three dimensions rather than confined to a single plane.
Solution Approach 2:
The patent divides the bit line connections into multiple segments arranged in different layers. Lower bit lines are positioned at first vertical levels and upper bit lines at second vertical levels, with each layer serving specific memory cell regions. This segmentation of connection paths reduces interference and manages the complexity of three-dimensional wiring by organizing conductors into distinct vertical strata.
2Quantity of substance
If channel holes are arranged at narrow pitch to increase data storage capacity, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves narrow pitch arrangement of channel holes by extending channels vertically through multiple gate electrode layers. Instead of packing more channels horizontally in a single layer, the invention utilizes the vertical dimension to create multiple channels that penetrate through stacked gate structures, effectively increasing channel density without requiring proportionally tighter horizontal spacing.
3Quantity of substance
If multiple layers of bit lines are used to connect channel structures, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-layer bit line structures where lower bit lines and upper bit lines are positioned at different vertical levels. This vertical stacking of conductive layers enables independent connection to different sets of channel structures, effectively multiplying the storage capacity by creating separate addressable memory regions without requiring proportional increases in planar wiring complexity.
Solution Approach 2:
The bit line system is segmented into lower and upper layers, each serving specific memory cell regions. Lower bit lines connect to channel structures in first regions while upper bit lines connect to channel structures in second regions. This segmentation allows independent control and addressing of different memory regions, managing the complexity of three-dimensional connections by creating modular, layer-specific connection schemes.
Data Source
AI summary
A semiconductor device may include a plurality of gate electrodes apart from each other in a vertical direction on a substrate; a plurality of channel structures penetrating the plurality of gate electrodes and extending in the vertical direction; and a plurality of bit lines arranged on and connected to the plurality of channel structures. The plurality of bit lines may include a plurality of lower bit lines and a plurality of upper bit lines at different vertical levels from each other to constitute at least two layers. The plurality of upper bit lines may be apart from each other in a first horizontal direction and extend in parallel with each other in a second horizontal direction perpendicular to the first horizontal direction. A lower expansion space may be defined between two lower bit lines adjacent to each other among the plurality of lower bit lines.