Vertical BJT Access Element for High Density Memory
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Solution Overview
Problem
Conventional cross-point RRAM architectures suffer from slow read access due to parasitic current leakage through non-selected memory cells, which is exacerbated by the significant area consumption of conventional access elements, limiting memory array density.
Innovation Solution
The use of vertical bipolar junction transistors (BJTs) as access elements reduces current leakage and area consumption, enabling a denser memory array layout by selectively coupling a source line to data storage elements based on word line voltage, thereby improving read access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional access elements are used in cross-point RRAM architecture, then current leakage is suppressed, but chip area consumption increases significantly
Solution Approach 1:
The access element transitions from a planar two-dimensional layout to a vertical three-dimensional structure. The BJT is positioned vertically above the cross-point, with its collector extending downward toward the storage element and its base and emitter forming a vertical transistor structure. This vertical arrangement suppresses lateral current leakage paths while occupying minimal planar area, effectively resolving the contradiction between leakage suppression and area consumption.
2Quantity of substance
If cross-point array architecture is used, then memory density is increased, but read access speed decreases due to parasitic current
Solution Approach 1:
The vertical BJT acts as an intermediary access element between the word line/bit line and the resistive storage element. It provides selective electrical connection to the storage element based on applied voltages, enabling precise control of current flow. This intermediary structure allows the cross-point architecture to maintain high density while achieving fast read access by preventing parasitic current through non-selected cells and enabling rapid selective access to targeted elements.
3Area of stationary object
If vertical BJT access elements are used, then area consumption is reduced and memory density is increased, but device complexity increases
Solution Approach 1:
The vertical BJT structure serves multiple functions simultaneously: it acts as a selective access element for row decoding, provides current amplification for low-power operation, suppresses parasitic leakage paths, and enables high-density packing. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in overall device complexity despite the vertical three-dimensional configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory storage density and reduces current leakage, leading to faster read access and higher data storage capacity without increasing chip area.
Implementation Method 1
vertical bipolar junction transistors (BJTs) that can be used as access elements
Data Source
AI summary
Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.