Vertical BJT Array Layout for Scalable RRAM Bitcells
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Solution Overview
Problem
Existing resistive random-access memory (RRAM) devices face limitations in scalability due to the minimum voltage and drive current requirements imposed on field-effect transistors, which restrict the ability to shrink bitcell dimensions.
Innovation Solution
The proposed structure includes an array of bipolar junction transistors (BJTs) with trench isolation regions and base layers extending across these regions, allowing for the formation of compact BJTs that can serve as access transistors in RRAM devices, thereby eliminating the need for field-effect transistors and enhancing scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistor designs are used, then manufacturing is simpler, but power consumption increases and switching speed decreases
Solution Approach 1:
The patent transitions from planar (2D) transistor designs to vertical (3D) transistor structures. The vertical bipolar junction transistor (vBJT) architecture stacks multiple transistor layers vertically, enabling higher integration density while reducing power consumption and improving switching speed compared to conventional planar designs.
Solution Approach 2:
The patent implements nested transistor structures where multiple transistor layers are stacked vertically within a compact footprint. Each transistor layer is nested within the vertical structure, allowing multiple functional layers to occupy the same lateral space while maintaining electrical isolation and individual functionality.
2Device complexity
If planar transistor designs are used, then device structure is simpler, but switching speed decreases
Solution Approach 1:
The vertical transistor architecture reduces the current path length by stacking layers vertically, thereby decreasing the base width and improving carrier transport efficiency. This dimensional change enables faster switching speeds while maintaining manageable structural complexity through standardized vertical fabrication processes.
3Quantity of substance
If higher transistor density is achieved through vertical stacking, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The vertical transistor structure is divided into discrete functional layers (emitter, base, collector) that can be fabricated and aligned independently. This segmentation allows for standardized layer thicknesses and simplified alignment processes, reducing the overall manufacturing precision requirements despite the increased integration density.
Solution Approach 2:
The patent optimizes vertical layer thickness parameters and doping profiles to achieve high integration density while maintaining manufacturability. By carefully controlling layer thicknesses and material compositions, the design achieves dense packing without requiring excessive manufacturing precision.
Data Source
Figure 1
Figure 2~2A
Figure 3~3A
AI summary
Structures that include bipolar junction transistors and methods of forming such structures. The structure (10) comprises a substrate (32) having a top surface, a trench isolation region (24) in the substrate, and a base layer (20) on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor (12) includes a first collector (34) in the substrate and a first emitter (40) on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor (16) includes a second collector (36) in the substrate and a second emitter (44) on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.