Vertical Body Contact Structure for 3D Memory Leakage Control
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high circuit density, reduced operational latency, and improved data retention due to floating body effects and leakage currents, which degrade memory cell performance and increase power consumption.
Innovation Solution
The implementation of a 3D semiconductor device with a vertical body contact structure, featuring a gate-all-around (GAA) thin-film transistor (TFT) configuration and a vertically extending body contact that connects multiple layers, reducing floating body effects and enhancing current flow by allowing higher doping and isolating leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar semiconductor structures are used, then manufacturing is simpler, but circuit density and data retention are limited due to floating body effects
Solution Approach 1:
The patent transitions from conventional planar (2D) semiconductor structures to three-dimensional vertically stacked structures. Multiple transistor layers are stacked vertically with shared body contacts, creating a 3D architecture that increases circuit density while the vertical body contact extends through multiple layers to reduce floating body effects and improve data retention.
2Power
If higher doping is used to increase on-current, then 'on' current increases, but leakage current also increases
Solution Approach 1:
The patent applies different doping concentrations to different regions of the semiconductor structure. Higher doping is used in the body contact regions to increase on-current, while the channel regions maintain appropriate doping levels to minimize leakage. The vertical body contact structure allows localized high doping without proportionally increasing leakage across the entire device.
3Area of stationary object
If circuit density is increased to reduce device footprint, then area is reduced, but floating body effects worsen
Solution Approach 1:
The patent stacks multiple transistor layers vertically to increase circuit density within a reduced footprint. The vertical body contact extends through multiple stacked layers, providing continuous electrical connection that eliminates floating body effects even in the compact 3D configuration. This allows high density without sacrificing reliability.
4Use of energy by stationary object
If refresh rate is reduced to lower power consumption, then power decreases, but data retention becomes insufficient
Solution Approach 1:
The patent converts the typically harmful floating body effects into a beneficial structure by implementing vertical body contacts that extend through stacked layers. This structure actively collects and removes accumulated charge that would otherwise cause leakage, thereby improving data retention and enabling lower refresh rates and reduced power consumption.
Data Source
AI summary
Methods, apparatuses, and systems related to a memory device having transistor body contacts that extend vertically across stacked circuit layers and connect to body portions of data access transistors are described. A memory device may include storage cells and corresponding access circuits on each of the stacked layers. The vertically extending transistor body contacts may provide a route for leakage away from data storage circuits when the data access transistors are off.