Vertical Bond Pads for Compact Semiconductor Die Stacking

Solution Overview

Problem

The increasing demand for high-capacity storage in portable consumer electronics is limited by the length of stacked semiconductor dies due to conventional stepped, offset configurations, which restrict the number and length of dies that can be included in a semiconductor package.

Innovation Solution

The implementation of semiconductor dies with vertical bond pads on their edges, allowing for direct stacking and vertical wire bonding without offset, thereby eliminating the length constraint and enabling more dies to be packed within a given size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional stepped, offset configurations are used for stacking semiconductor dies, then access to die bond pads is enabled, but the overall length of the die stack increases, limiting the number of dies that can be included

Engineering Contradiction:

Improveaccess to die bond padsVSAvoidoverall length of die stack

Core Design Contradiction:

Ease of operationVSLength of moving object

Solution Approach 1:

The patent inverts the conventional bonding approach by moving the bond pads from the top surface of each die to the vertical edge of the die. This inversion allows wires to be bonded vertically to the edge pads rather than horizontally across offset surfaces, eliminating the need for stepped configurations and reducing the overall package length.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from two-dimensional top-surface bonding to three-dimensional edge bonding. By placing bond pads on the vertical edge of the dies and performing wire bonding in the vertical dimension, the patent eliminates the horizontal offset requirement, allowing compact stacking without increasing package length.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If more semiconductor dies are stacked together to increase storage capacity, then storage capacity increases, but the package size increases due to stepped offset configurations

Engineering Contradiction:

Improvenumber of semiconductor diesVSAvoidpackage size

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent inverts the conventional bonding approach by moving the bond pads from the top surface of each die to the vertical edge of the die. This inversion allows wires to be bonded vertically to the edge pads rather than horizontally across offset surfaces, eliminating the need for stepped configurations and reducing the overall package length.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from two-dimensional top-surface bonding to three-dimensional edge bonding. By placing bond pads on the vertical edge of the dies and performing wire bonding in the vertical dimension, the patent eliminates the horizontal offset requirement, allowing compact stacking without increasing package length.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Length of moving object

If vertical bond pads are implemented on die edges, then direct stacking without offset is enabled, but additional fabrication steps are required during wafer processing

Engineering Contradiction:

Improvepackage lengthVSAvoidfabrication process complexity

Core Design Contradiction:

Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent performs preliminary actions during wafer fabrication by forming the vertical bond pad structures, cavities, and conductive fillings before dicing the wafer into individual dies. This preliminary preparation integrates the VBP structures into the standard fabrication process flow, making the additional manufacturing steps manageable despite increased process complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11222865B2Semiconductor device including vertical bond pads

Publication Date: 2022.01.11 SANDISK TECHNOLOGIES LLC

AI summary

The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.