Vertical Bus Circuit Galvanic Isolation for Battery Management

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Solution Overview

Problem

Conventional battery management systems face high costs due to expensive opto-couplers and high-voltage diodes, and potential damage from negative voltage spikes during connection breaks, which are not effectively addressed by existing isolation methods.

Innovation Solution

The implementation of a battery management system using passive galvanic isolators, such as capacitors, and a vertical bus circuit with differential input/output signals to protect chips from high voltages and facilitate communication between battery management chips, reducing costs and preventing chip damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If opto-couplers are used to isolate the common bus from high voltage potential, then the bus is protected from high voltage damage, but the system cost increases significantly

Engineering Contradiction:
Improvebus isolation from high voltageVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive opto-couplers with inexpensive high-voltage diodes for bus isolation. The diodes serve as a cost-effective protective element that can be easily replaced if needed, eliminating the need for costly opto-coupler components while maintaining the isolation function.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent substitutes the optical isolation mechanism (opto-couplers) with an electrical isolation mechanism using high-voltage diodes. This replacement simplifies the system by eliminating optical components and using straightforward electrical components that achieve the same protective function at lower cost.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If high-voltage diodes are used to protect battery management chips from negative voltage spikes, then chip damage is prevented, but the response time is too slow and chips may be damaged before protection activates

Engineering Contradiction:
Improvechip protection from negative voltageVSAvoidprotection response time
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces a capacitor as an intermediary protective element between the battery management chip and the high-voltage environment. The capacitor acts as a first line of defense that responds instantaneously to voltage spikes, providing immediate protection while the diode circuit activates as a secondary protective measure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements preliminary protection by placing capacitors in parallel with the battery management chips before any fault occurs. These capacitors are pre-positioned to immediately counteract negative voltage spikes the moment they occur, eliminating the response time delay associated with diode activation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If high-voltage diodes are used for chip protection, then negative voltage protection is provided, but the operating power consumption increases due to required forward conduction current

Engineering Contradiction:
Improvechip protection from negative voltageVSAvoidoperating power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent uses capacitors as intermediary energy storage elements that provide protection without requiring continuous current flow. The capacitors store energy and release it only when needed during voltage spikes, eliminating the continuous power consumption required by forward-biased diodes while maintaining protective functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces system costs, minimizes noise, and ensures continuous communication even in abnormal conditions, while effectively isolating battery management chips from high voltages, thus protecting them from damage.

Implementation Method 1

a first communication circuit and a second communication circuit, respectively, coupled to the converter and the vertical bus circuit. The battery management chip further includes a galvanic isolator to electrically isolate the first communication circuit from the second communication circuit

Methodology Applied
Scientific EffectGalvanic isolation: Electrical Impedance Tomography

Implementation Method 2

The implementation of a battery management system using passive galvanic isolators, such as capacitors

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

a vertical bus circuit with differential input/output signals to protect chips from high voltages and facilitate communication between battery management chips

Methodology Applied
Scientific EffectDifferential signaling: Electromagnetic Induction

Data Source

PatentUS8907625B2Battery management systems with vertical bus circuits
Publication Date: 2014.12.09 O2 MICRO INT LTD
  • US8907625B2 patent drawing
  • US8907625B2 patent drawing
  • US8907625B2 patent drawing

AI summary

A battery management chip may include a battery management unit and a vertical bus circuit. The battery management unit can monitor a cell status of multiple cells in a battery module coupled to the battery management chip in response to an instruction from a host processor. The vertical bus circuit may transfer the instruction from the host processor to the battery management unit. The vertical bus circuit may include a first receiver, a command processor and a first transmitter. The first receiver can receive a first pair of differential input data signals. The command processor can process the first pair of differential input data signals. The first transmitter can output a first pair of differential output data signals.