Vertical Capacitor Structure for High-Density 3D-NAND Integration
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Solution Overview
Problem
Current capacitor structures in 3D-NAND technology face challenges in achieving high capacitance density while maintaining a small footprint, as they require additional chip area and are prone to time-dependent dielectric breakdown, which is exacerbated by the increasing number of devices and metal lines in advanced architectures like 64L to 128L.
Innovation Solution
A novel vertical-type capacitor structure is introduced, where conductive plates extend from the top to the bottom surface of the substrate, with a concentric arrangement and insulating structure in between, allowing for high capacitance density in a reduced chip area and preventing electrical interference with adjacent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional flat parallel plate capacitor structures are used, then the capacitor can store electric energy, but additional chip areas are required to achieve high capacitance density
Solution Approach 1:
The patent transitions from traditional planar parallel plate capacitors to a vertical cylindrical capacitor structure. The conductive plates are arranged concentrically around a central axis, extending vertically through the substrate, utilizing the third dimension (height/depth) to achieve high capacitance density without increasing chip area. This dimensional change allows the capacitor to occupy minimal footprint while maximizing storage capacity through vertical stacking and radial plate arrangement.
2Quantity of substance
If MOS/MOM capacitors are used to meet circuit requirements, then capacitance density is achieved, but the time-dependent dielectric breakdown failure rate increases
Solution Approach 1:
The patent employs a composite dielectric structure consisting of multiple layers including silicon oxide, silicon nitride, and other insulating materials. This multi-layer composite dielectric architecture enhances the overall breakdown strength and reliability of the capacitor while maintaining high capacitance density. The different material layers provide complementary properties that resist time-dependent dielectric breakdown better than single-material capacitors.
3Quantity of substance
If the number of devices and metal lines increases in 64L to 128L architecture, then storage capacity increases, but the space for introducing capacitors decreases
Solution Approach 1:
The patent implements a nested concentric cylindrical structure where multiple conductive plates are arranged one inside another around a central axis, similar to nested dolls. This nested configuration allows multiple capacitor elements to be packed into a compact vertical space, maximizing the use of available volume while minimizing the horizontal footprint. The structure enables high capacitance density in a space-efficient manner that accommodates the reduced available area in advanced 128L architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides high capacitance density, reduces chip area occupancy, and minimizes the risk of electrical failure, effectively meeting the scaling requirements of advanced memory technologies.
Implementation Method 1
an insulating structure that is formed between the first conductive plate and the second conductive plate and extends from the first main surface to the second main surface
Data Source
AI summary
A capacitor is provided. The capacitor includes a substrate, at least two conductive plates formed in the substrate and extending into the substrate, at least one insulating structure formed between two adjacent conductive plates of the at least two conductive plates and extending into the substrate, and a plurality of contacts, each extending into respective one of the at least two conductive plates.