Vertical Capacitor Contact Arrangement with Dummy Planarization
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Solution Overview
Problem
High-density imaging arrays face challenges in achieving low noise equivalent differential temperature (NEDT) due to the limitations of small pixel size, which reduces charge storage capacity, and issues with overetching and breaching of dielectric layers in vertical capacitors, leading to reduced breakdown voltage and plating non-uniformity.
Innovation Solution
A contact arrangement for vertical capacitors on integrated circuits, featuring a T-shaped recess for accessing top metal layers and the use of dummy capacitors to ensure uniform planarization, preventing overetching and maintaining reliable electrical contact with copper metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pixel size is reduced to achieve high-density imaging arrays, then the array density increases, but the charge storage capacitor size decreases leading to reduced charge storage capacity and increased NEDT
Solution Approach 1:
The patent transitions from planar capacitors to vertical capacitors, utilizing the third dimension (depth) to increase capacitor volume and charge storage capacity while maintaining a small pixel footprint. The vertical capacitor structure extends downward into the substrate, allowing sufficient charge storage volume within constrained lateral dimensions.
2Ease of operation
If conventional etching processes are used to access capacitor metal layers, then electrical contact can be made, but overetching occurs breaching the dielectric layer and causing reduced breakdown voltage and shorting
Solution Approach 1:
The patent applies a planarization oxide layer and performs chemical-mechanical planarization (CMP) before etching the contact recesses. This preliminary planarization creates a uniform surface that prevents overetching by ensuring the etch process stops at the intended depth, preventing breaching of the dielectric layer between capacitor plates.
3Shape
If standard planarization is applied to capacitor arrays with sharp edges, then surface smoothing occurs, but extra thin layer of planarization oxide forms at edges creating non-uniformity
Solution Approach 1:
The patent introduces dummy capacitors at the edges of the capacitor array to match the height of the main capacitor array. This local modification ensures uniform planarization oxide thickness across the entire array by providing consistent topography at edges, preventing the formation of extra thin oxide layers and maintaining manufacturing precision.
Data Source
AI summary
An arrangement for making electrical contact to a vertical capacitor having top and bottom metal layers separated by a dielectric, and at least one trench. Recesses are formed in an oxide layer over the capacitor to provide access to the top and bottom metal layers. The recesses include contacting portions preferably positioned such that there is no overlap between them and any of the trenches. Metal in the recesses, preferably copper, forms electrical contacts to the vertical capacitor's metal layers and enables reliable bonding to copper metallization on other layers such as an ROIC layer. ‘Dummy’ capacitors may be tiled on portions of the IC where there are no vertical capacitors, preferably with the top surfaces of their top metal at a height approximately equal to that of the top surface of the vertical capacitor's top metal, thereby enabling the IC to be planarized with a uniform planarization thickness.