Vertical Capacitor Electrodes for High-Density Memory
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Solution Overview
Problem
The integration density of semiconductor memory devices is limited by the large area occupied by peripheral circuit capacitors in non-volatile memory devices with vertical memory cell structures, requiring increased pump capacity and reduced integration density.
Innovation Solution
The implementation of vertical capacitors in the peripheral circuit region, with capacitor electrodes extending through an insulating layer and spaced apart to reduce area occupancy, allowing for higher integration density and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar capacitors are used in the peripheral circuit region, then the capacitor can provide sufficient pump capacity, but the area occupied by the capacitor becomes very large
Solution Approach 1:
The patent transforms the capacitor structure from a planar two-dimensional layout to a vertical three-dimensional configuration. The capacitor electrodes extend in the vertical direction (first direction) through the insulating layer, allowing the capacitor to achieve sufficient pump capacity while occupying minimal planar area. This dimensional change enables the peripheral circuit region to provide the required capacitance without increasing the overall device footprint.
Solution Approach 2:
The vertical capacitor electrodes are nested within the peripheral circuit region, extending through the insulating layer while maintaining close spacing. Multiple capacitor electrodes can be arranged in a compact vertical configuration, effectively nesting the capacitor structure within the available space of the peripheral circuit region, thereby maximizing space utilization.
2Area of stationary object
If vertical capacitor electrodes are used, then the area occupied by the capacitor is reduced, but the manufacturing complexity increases
Solution Approach 1:
The capacitor structure is segmented into multiple discrete electrodes that extend vertically through the insulating layer. These segmented electrodes can be independently formed and positioned, allowing for systematic manufacturing. The segmentation enables the vertical capacitor structure to be integrated into the existing fabrication process flow without requiring entirely new manufacturing techniques.
Data Source
AI summary
Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.