Vertical Parallel Plate Capacitor Structure for Integrated Circuits
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Solution Overview
Problem
Conventional vertical parallel plate capacitors in semiconductor devices face reliability issues due to misalignment in lithography processes and leakage currents caused by thin or incomplete dielectric liners in small-sized vias, leading to early dielectric breakdown and reduced capacitance density.
Innovation Solution
The development of novel vertical parallel plate capacitor structures with multiple via levels, where metal bars are used instead of metal lines for capacitive coupling, increasing capacitance density and reliability by avoiding misalignment and leakage issues through the use of longer metal bars and vias, and insulating layers to prevent shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional vertical parallel plate capacitors are used with small-sized vias, then capacitance density can be increased, but misalignment in lithography processes and leakage currents occur leading to early dielectric breakdown
Solution Approach 1:
The capacitor structure is divided into multiple via levels (first via level, second via level) with insulating layers between them. This segmentation allows each via level to be independently formed and controlled, preventing the misalignment and leakage issues that occur in conventional single-level structures while maintaining high capacitance density through the stacked configuration.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the first and second via levels. These insulating layers act as mediators that prevent direct electrical contact between adjacent via levels, eliminating leakage current paths while allowing the capacitive coupling to function. This resolves the contradiction by providing dielectric isolation without requiring smaller via dimensions that would exacerbate alignment issues.
2Reliability
If metal lines are used to couple capacitor plates, then capacitance density is reduced due to direct coupling, but using longer metal bars and multiple via levels increases reliability
Solution Approach 1:
The capacitor structure transitions from a planar configuration to a three-dimensional stacked configuration with multiple via levels. By adding the vertical dimension with insulating layers between via levels, the structure achieves both high capacitance density (through increased plate area in 3D space) and high reliability (through dielectric isolation preventing leakage), resolving the contradiction between these two parameters.
3Quantity of substance
If thin dielectric liners are used in small-sized vias, then via size can be reduced for higher capacitance density, but leakage currents and incomplete dielectric coverage occur
Solution Approach 1:
The via structure is segmented into multiple levels with insulating layers between them. This segmentation allows each via level to be formed with adequate dielectric coverage and thickness, avoiding the manufacturing precision issues that occur when attempting to form thin, complete liners in single small-sized vias. The segmented approach maintains high capacitance density while ensuring complete and reliable dielectric insulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and capacitance density of capacitors by eliminating misalignment and leakage current issues, while maintaining the integrity of insulating layers to prevent shorting and dielectric breakdown.
Implementation Method 1
An insulating layer is disposed in a metal line level between the first metal bars and the second metal bars
Implementation Method 2
Capacitors essentially comprise two conductive plates separated by an insulating material. When an electric current is applied to a capacitor, electric charges of equal magnitude yet opposite polarity build up on the capacitor plates
Data Source
AI summary
A capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.