Vertical Capacitor Integration in Electronic Device Packages
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Solution Overview
Problem
Modern electronic device packages are hindered by performance deficiencies, large size, and high manufacturing costs due to inefficient capacitor placement and electromagnetic interference.
Innovation Solution
The strategic placement of thin film capacitors under and on top of the inductor, within the dielectric substrate, and directly on the controller chip, along with the use of microvias and thermal pads, reduces the size and enhances heat dissipation, while minimizing parasitic inductance and connection path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If capacitors are placed side-by-side on the substrate with the controller chip, then the package can accommodate all components, but the package size becomes large and the connection path length increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of components to a three-dimensional vertical stacking configuration. The controller chip is positioned at the bottom layer, with input and output capacitors stacked vertically above it on the same substrate. This vertical integration dramatically reduces the horizontal footprint of the package while maintaining all necessary electrical connections through vias and conductive pathways in the substrate.
2Reliability
If capacitors are placed closer to the controller chip to reduce connection path length, then parasitic inductance is reduced, but the package layout becomes more complex
Solution Approach 1:
The patent merges the capacitor and controller chip into a single integrated package unit, with capacitors mounted directly on the substrate in close proximity to the controller chip. This integration eliminates the need for separate external capacitor mounting areas and reduces the overall connection path length. The electrical connections are established through direct soldering or conductive pathways within the substrate, minimizing parasitic inductance while simplifying the overall system architecture.
3Ease of manufacture
If traditional capacitor placement is used, then manufacturing is simpler, but electromagnetic interference and noise are generated due to high frequency switching
Solution Approach 1:
The patent addresses electromagnetic interference by strategically placing the input capacitor as close as possible to the controller chip's power input terminals and the output capacitor near the output terminals. This minimizes the loop area for high-frequency switching currents, thereby reducing radiated electromagnetic interference. Additionally, the vertical stacking configuration shortens trace lengths and reduces parasitic effects, converting the potential harm of high-frequency switching into a benefit by minimizing its negative impacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in smaller, more cost-effective, and improved-performing electronic device packages with enhanced heat dissipation and reduced electromagnetic interference.
Implementation Method 1
the first capacitor directly on a first surface of the controller chip and the second capacitor directly on a second surface of the controller chip
Implementation Method 2
placing a thermal pad adjacent to a capacitor at the bottom surface of the dielectric substrate, thus enhancing the heat dissipation rate of the package
Data Source
AI summary
A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation.