Vertical Capacitor Structure for High Density and Reliability

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Solution Overview

Problem

The challenge in semiconductor devices is to increase capacitance per unit area while minimizing inductive and resistive losses, as the size of unit cells decreases and the interval between comb-structured conductive pattern layers in conventional vertical natural capacitors (VNCAPs) becomes finer, leading to potential breakdown, short circuits, and current leakage.

Innovation Solution

The capacitor structure is designed with conductive pattern layers and contact layers at different vertical levels, avoiding direct electrical connection during the formation process, which reduces the likelihood of voltage differences and subsequent issues like breakdown or short circuits, by using a via plug and contact plug to establish connections at distinct levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the interval between comb-structured conductive pattern layers is reduced to increase capacitance per unit area, then the capacitance per unit area increases, but the risk of breakdown, short circuits, and current leakage increases

Engineering Contradiction:
Improvecapacitance per unit areaVSAvoidrisk of breakdown and short circuits
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a planar capacitor structure to a vertical three-dimensional structure by stacking multiple conductive pattern layers at different heights. This vertical stacking increases capacitance per unit area without reducing the horizontal interval between layers, thereby maintaining reliability while achieving higher capacitance density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor is divided into multiple discrete conductive pattern layers (first, second, third, and fourth conductive pattern layers) separated by dielectric layers. This segmentation allows each layer to be independently formed and positioned, enabling vertical stacking with adequate spacing to prevent breakdown and short circuits while increasing overall capacitance.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conductive pattern layers are formed at the same level as contact layers, then the manufacturing process is simplified, but voltage differences cause breakdown, short circuits, and current leakage

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidelectrical connection stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent positions contact layers at a different vertical level (height) than the conductive pattern layers. Specifically, the contact layer is formed at a higher level than the fourth conductive pattern layer, eliminating direct electrical connection and preventing voltage-related breakdown and short circuits while maintaining manufacturing simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Dielectric layers serve as intermediaries between the conductive pattern layers and contact layers. These dielectric layers electrically isolate the conductive pattern layers from the contact layer, preventing direct electrical connection and the associated reliability issues, while still allowing the manufacturing process to remain straightforward.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10522456B2Capacitor structure and semiconductor device including the same
Publication Date: 2019.12.31 SAMSUNG ELECTRONICS CO LTD
  • US10522456B2 patent drawing
  • US10522456B2 patent drawing
  • US10522456B2 patent drawing

AI summary

A capacitor structure includes a substrate including an electrode pad and a ground pad, a plurality of dielectric layers on the substrate, the plurality of dielectric layers being at different levels on the substrate, a plurality of conductive pattern layers in at least two dielectric layers of the plurality of dielectric layers, the at least two dielectric layers of the plurality of dielectric layers being first dielectric layers, a plurality of via plugs connecting the plurality of conductive pattern layers to each other, and at least one contact layer in at least one second dielectric layer of the plurality of dielectric layers, the at least one second dielectric layer being different from the at least two first dielectric layers, and the at least one contact layer electrically connecting the plurality of conductive pattern layers to the electrode pad and the ground pad.